LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 308
LPC1112FHN33/203,5
Manufacturer Part Number
LPC1112FHN33/203,5
Description
ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
Manufacturer
NXP Semiconductors
Datasheet
1.LPC1113FHN333035.pdf
(538 pages)
Specifications of LPC1112FHN33/203,5
Rohs
yes
Core
ARM Cortex M0
Processor Series
LPC1112
Data Bus Width
32 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
16 KB
Data Ram Size
4 KB
On-chip Adc
Yes
Operating Supply Voltage
1.8 V to 3.6 V
Operating Temperature Range
- 65 C to + 150 C
Package / Case
HVQFN-33
Mounting Style
SMD/SMT
Factory Pack Quantity
260
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NXP Semiconductors
UM10398
User manual
16.7.4 Interrupt handling
If several interrupts are pending, the CAN Interrupt Register will point to the pending
interrupt with the highest priority, disregarding their chronological order. An interrupt
remains pending until the CPU has cleared it.
Fig 65. Reading a message from the FIFO buffer to the message buffer
INTID = 0x8000 ?
interrupt handling
status change
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
yes
write MessageNum to CANIFx_CMDREQ
MessageNum = MessageNum +1
read message to message buffer
read data from CANIFx_DA/B
MessageNum = INTID
read CANIFx_MCTRL
Chapter 16: LPC111x/LPC11Cxx C_CAN controller
reset NEWDAT = 0
reset INTPND = 0
INTID = 0x0001
NEWDAT = 1
read CANIR
to 0x0020 ?
EOB = 1
START
no
yes
yes
no
yes
INTID = 0x0000 ?
END
UM10398
yes
© NXP B.V. 2012. All rights reserved.
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