LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 143

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
9.5 LPC111x/LPC11Cxx Pin description
Table 159. LPC1113/14 and LPC11C12/C14 pin description table (LQFP48 package)
UM10398
User manual
Symbol
PIO0_0 to PIO0_11
RESET/PIO0_0
PIO0_1/CLKOUT/
CT32B0_MAT2
PIO0_2/SSEL0/
CT16B0_CAP0
PIO0_3
PIO0_4/SCL
PIO0_5/SDA
PIO0_6/SCK0
PIO0_7/CTS
PIO0_8/MISO0/
CT16B0_MAT0
PIO0_9/MOSI0/
CT16B0_MAT1
SWCLK/PIO0_10/
SCK0/CT16B0_MAT2
Pin
3
4
10
14
15
16
22
23
27
28
29
[1][2]
[3][2]
[3][2]
[3][2]
[4][2]
[4][2]
[3][2]
[3][2]
[3][2]
[3][2]
[3][2]
Type
I/O
I
I/O
I/O
O
O
I/O
O
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I/O
I/O
O
I/O
I/O
O
I
I/O
I/O
O
Chapter 9: LPC111x/LPC11Cxx Pin configuration (LPC1100, LPC1100C,
All information provided in this document is subject to legal disclaimers.
Description
Port 0 — Port 0 is a 12-bit I/O port with individual direction and function
controls for each bit. The operation of port 0 pins depends on the function
selected through the IOCONFIG register block.
RESET — External reset input: A LOW on this pin resets the device,
causing I/O ports and peripherals to take on their default states, and
processor execution to begin at address 0.
PIO0_0 — General purpose digital input/output pin.
PIO0_1 — General purpose digital input/output pin. A LOW level on this pin
during reset starts the flash ISP command handler via UART (if PIO0_3 is
HIGH) or via C_CAN (if PIO0_3 is LOW).
CLKOUT — Clockout pin.
CT32B0_MAT2 — Match output 2 for 32-bit timer 0.
PIO0_2 — General purpose digital input/output pin.
SSEL0 — Slave Select for SPI0.
CT16B0_CAP0 — Capture input 0 for 16-bit timer 0.
PIO0_3 — General purpose digital input/output pin. This pin is monitored
during reset: Together with a LOW level on pin PIO0_1, a LOW level starts
the flash ISP command handler via C_CAN and a HIGH level starts the
flash ISP command handler via UART.
PIO0_4 — General purpose digital input/output pin (open-drain).
SCL — I
Fast-mode Plus is selected in the I/O configuration register.
PIO0_5 — General purpose digital input/output pin (open-drain).
SDA — I
Fast-mode Plus is selected in the I/O configuration register.
PIO0_6 — General purpose digital input/output pin.
SCK0 — Serial clock for SPI0.
PIO0_7 — General purpose digital input/output pin (high-current output
driver).
CTS — Clear To Send input for UART.
PIO0_8 — General purpose digital input/output pin.
MISO0 — Master In Slave Out for SPI0.
CT16B0_MAT0 — Match output 0 for 16-bit timer 0.
PIO0_9 — General purpose digital input/output pin.
MOSI0 — Master Out Slave In for SPI0.
CT16B0_MAT1 — Match output 1 for 16-bit timer 0.
SWCLK — Serial wire clock.
PIO0_10 — General purpose digital input/output pin.
SCK0 — Serial clock for SPI0.
CT16B0_MAT2 — Match output 2 for 16-bit timer 0.
Rev. 12 — 24 September 2012
2
2
C-bus, open-drain clock input/output. High-current sink only if I
C-bus, open-drain data input/output. High-current sink only if I
UM10398
© NXP B.V. 2012. All rights reserved.
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