LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 325

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

18.1 How to read this chapter
18.2 Basic configuration
18.3 Features
UM10398
User manual
The 16-bit timer blocks are identical for all LPC111x, LPC11D14, and LPC11Cxx parts in
the LPC1100, LPC1100C, and LPC1100L series.
Pin-out variations
The match output MAT0 of timer 1 (CT16B1_MAT0) is not pinned out on parts LPC11C22
and LPC11C24.
The CT16B0/1 are configured using the following registers:
1. Pins: The CT16B0/1 pins must be configured in the IOCONFIG register block
2. Power and peripheral clock: In the SYSAHBCLKCTRL register, set bit 7 and bit 8
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UM10398
Chapter 18: LPC1100/LPC1100C/LPC1100L series: 16-bit
counter/timer CT16B0/1
Rev. 12 — 24 September 2012
(Section
(Table
Two 16-bit counter/timers with a programmable 16-bit prescaler.
Counter or timer operation.
One 16-bit capture channel that can take a snapshot of the timer value when an input
signal transitions. A capture event may also optionally generate an interrupt.
Four 16-bit match registers that allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
Up to three (CT16B0) or two (CT16B1) external outputs corresponding to match
registers with the following capabilities:
– Set LOW on match.
– Set HIGH on match.
– Toggle on match.
– Do nothing on match.
For each timer, up to four match registers can be configured as PWM allowing to use
up to three match outputs as single edge controlled PWM outputs.
21). The peripheral clock is provided by the system clock (see
7.4).
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
© NXP B.V. 2012. All rights reserved.
Table
User manual
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