LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 98

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
7.4.43 IOCON_SCK_LOC
7.4.44 IOCON_DSR_LOC
Table 98.
Table 99.
Table 100. IOCON DSR location register (IOCON_DSR_LOC, address 0x4004 40B4) bit
Bit
10
31:11
Bit
1:0
31:2
Bit
1:0
31:2
Symbol
OD
-
Symbol
SCKLOC
-
Symbol
DSRLOC
-
IOCON_PIO3_3 register (IOCON_PIO3_3, address 0x4004 40AC) bit description
IOCON SCK location register (IOCON_SCK_LOC, address 0x4004 40B0) bit
description
description
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Value
0
1
-
Value
0x0
0x1
0x2
0x3
-
Value
0x0
0x1
0x2
0x3
-
Chapter 7: LPC1100/LPC1100C/LPC1100L series: I/O configuration
Rev. 12 — 24 September 2012
Open-drain output
Selects pin location for SCK0 function.
Selects SCK0 function in pin location PIO2_11/SCK0 (see
Selects SCK0 function in pin location PIO0_6/SCK0 (see
Reserved.
Selects pin location for DSR function.
Reserved.
Reserved.
Description
Selects pseudo open-drain mode. See
specific details.
Standard GPIO output
Reserved
Description
Selects SCK0 function in pin location
SWCLK/PIO0_10/SCK0/CT16B0_MAT2 (see
Table
Table
Reserved.
Description
Selects DSR function in pin location PIO2_1/DSR/SCK1.
Selects DSR function in pin location PIO3_1/DSR.
Reserved.
83.
74).
Section 7.1
Table
UM10398
© NXP B.V. 2012. All rights reserved.
for part
81).
98 of 538
00
Reset
value
0
-
Reset
value
00
-
Reset
value
-