LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 188

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
12.4 Functional description
UM10398
User manual
12.4.1 Write/read data operation
In order for software to be able to set GPIO bits without affecting any other pins in a single
write operation, bits [13:2] of a 14-bit wide address bus are used to create a 12-bit wide
mask for write and read operations on the 12 GPIO pins for each port. Only GPIOnDATA
bits masked by 1 are affected by read and write operations. The masked GPIOnDATA
register can be located anywhere between address offsets 0x0000 to 0x3FFC in the
GPIOn address space. Reading and writing to the GPIOnDATA register at address
0x3FFC sets all masking bits to 1.
Write operation
If the address bit (i+2) associated with the GPIO port bit i (i = 0 to 11) to be written is
HIGH, the value of the GPIODATA register bit i is updated. If the address bit (i+2) is LOW,
the corresponding GPIODATA register bit i is left unchanged.
Fig 29. Masked write operation to the GPIODATA register
at address + 0x098
GPIODATA register
ADDRESS[13:2]
address 0x098
All information provided in this document is subject to legal disclaimers.
data 0xFE4
Rev. 12 — 24 September 2012
u = unchanged
Chapter 12: LPC111x/LPC11Cxx General Purpose I/O (GPIO)
13
0
1
u
12
0
1
u
11
0
1
u
10
0
1
u
9
0
1
u
8
0
1
u
7
1
1
1
6
0
0
u
5
0
0
u
4
1
1
1
3
1
0
0
2
0
0
u
UM10398
© NXP B.V. 2012. All rights reserved.
0
0
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