LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 504

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
28.6.3.4 Application Interrupt and Reset Control Register
Table 450. ICSR bit assignments
[1]
[2]
When you write to the ICSR, the effect is Unpredictable if you:
The AIRCR provides endian status for data accesses and reset control of the system. See
the register summary in
To write to this register, you must write 0x05FA to the VECTKEY field, otherwise the
processor ignores the write.
The bit assignments are:
Bits
[25]
[24:23]
[22]
[21:18]
[17:12]
[11:6]
[5:0]
•
•
This is the same value as IPSR bits[5:0], see
See
write 1 to the PENDSVSET bit and write 1 to the PENDSVCLR bit
write 1 to the PENDSTSET bit and write 1 to the PENDSTCLR bit.
Section 28.1
Name
PENDSTCLR
-
ISRPENDING
-
VECTPENDING
-
VECTACTIVE
Chapter 28: LPC111x/LPC11Cxx Appendix: ARM Cortex-M0 reference
All information provided in this document is subject to legal disclaimers.
for implementation of the NMI for specific parts..
Rev. 12 — 24 September 2012
[1]
Table 28–448
Type
WO
-
RO
-
RO
-
RO
Function
SysTick exception clear-pending bit.
Write:
0 = no effect
1 = removes the pending state from the SysTick
exception.
This bit is WO. On a register read its value is Unknown.
Reserved.
Interrupt pending flag, excluding NMI and Faults:
0 = interrupt not pending
1 = interrupt pending.
Reserved.
Indicates the exception number of the highest priority
pending enabled exception:
0 = no pending exceptions
Nonzero = the exception number of the highest priority
pending enabled exception.
Reserved.
Contains the active exception number:
0 = Thread mode
Nonzero = The exception number
active exception.
Remark: Subtract 16 from this value to obtain the
CMSIS IRQ number that identifies the corresponding bit
in the Interrupt Clear-Enable, Set-Enable,
Clear-Pending, Set-pending, and Priority Register, see
Table
and
Table
28–422.
Table 28–451
28–422.
for its attributes.
[1]
UM10398
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