LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 223

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
14.6.7 SPI/SSP Raw Interrupt Status Register
14.6.8 SPI/SSP Masked Interrupt Status Register
Table 213: SPI/SSP Interrupt Mask Set/Clear register (SSP0IMSC - address 0x4004 0014,
This read-only register contains a 1 for each interrupt condition that is asserted,
regardless of whether or not the interrupt is enabled in the SSPIMSC registers.
Table 214: SPI/SSP Raw Interrupt Status register (SSP0RIS - address 0x4004 0018, SSP1RIS
This read-only register contains a 1 for each interrupt condition that is asserted and
enabled in the SSPIMSC registers. When an SPI interrupt occurs, the interrupt service
routine should read this register to determine the cause(s) of the interrupt.
Bit
0
1
2
3
31:4
Bit
0
1
2
3
31:4
Symbol
RORIM
RTIM
RXIM
TXIM
-
Symbol
RORRIS
RTRIS
RXRIS
TXRIS
-
SSP1IMSC - address 0x4005 8014) bit description
- address 0x4005 8018) bit description
All information provided in this document is subject to legal disclaimers.
Software should set this bit to enable interrupt when the Rx FIFO is at
This bit is 1 if another frame was completely received while the
Description
Software should set this bit to enable interrupt when a Receive
Overrun occurs, that is, when the Rx FIFO is full and another frame is
completely received. The ARM spec implies that the preceding frame
data is overwritten by the new frame data when this occurs.
Software should set this bit to enable interrupt when a Receive
Time-out condition occurs. A Receive Time-out occurs when the Rx
FIFO is not empty, and no has not been read for a time-out period.
The time-out period is the same for master and slave modes and is
determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR 
[SCR+1]).
least half full.
Software should set this bit to enable interrupt when the Tx FIFO is at
least half empty.
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Description
RxFIFO was full. The ARM spec implies that the preceding
frame data is overwritten by the new frame data when this
occurs.
This bit is 1 if the Rx FIFO is not empty, and has not been read
for a time-out period. The time-out period is the same for
master and slave modes and is determined by the SSP bit
rate: 32 bits at PCLK / (CPSDVSR  [SCR+1]).
This bit is 1 if the Rx FIFO is at least half full.
This bit is 1 if the Tx FIFO is at least half empty.
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Rev. 12 — 24 September 2012
Chapter 14: LPC111x/LPC11Cxx SPI0/1 with SSP
UM10398
© NXP B.V. 2012. All rights reserved.
Reset Value
0
0
0
1
NA
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Reset
Value
0
0
0
0
NA