LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 309

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
16.7.5 Bit timing
The Status Interrupt has the highest priority. Among the message interrupts, the Message
Object’s interrupt priority decreases with increasing message number.
A message interrupt is cleared by clearing the Message Object’s INTPND bit. The Status
Interrupt is cleared by reading the Status Register.
The interrupt identifier INTID in the Interrupt Register indicates the cause of the interrupt.
When no interrupt is pending, the register will hold the value zero. If the value of the
Interrupt Register is different from zero, then there is an interrupt pending and, if IE is set,
the interrupt line to the CPU, IRQ_B, is active. The interrupt line remains active until the
Interrupt Register is back to value zero (the cause of the interrupt is reset) or until IE is
reset.
The value 0x8000 indicates that an interrupt is pending because the CAN Core has
updated (not necessarily changed) the Status Register (Error Interrupt or Status Interrupt).
This interrupt has the highest priority. The CPU can update (reset) the status bits RXOK,
TXOK and LEC, but a write access of the CPU to the Status Register can never generate
or reset an interrupt.
All other values indicate that the source of the interrupt is one of the Message Objects
where INTID points to the pending message interrupt with the highest interrupt priority.
The CPU controls whether a change of the Status Register may cause an interrupt (bits
EIE and SIE in the CAN Control Register) and whether the interrupt line becomes active
when the Interrupt Register is different from zero (bit IE in the CAN Control Register). The
Interrupt Register will be updated even when IE is reset.
The CPU has two possibilities to follow the source of a message interrupt:
An interrupt service routine reading the message that is the source of the interrupt may
read the message and reset the Message Object’s INTPND at the same time (bit
ClrINTPND in the Command Mask Register). When INTPND is cleared, the Interrupt
Register will point to the next Message Object with a pending interrupt.
Even if minor errors in the configuration of the CAN bit timing do not result in immediate
failure, the performance of a CAN network can be reduced significantly. In many cases,
the CAN bit synchronization will amend a faulty configuration of the CAN bit timing to such
a degree that only occasionally an error frame is generated. In the case of arbitration
however, when two or more CAN nodes simultaneously try to transmit a frame, a
misplaced sample point may cause one of the transmitters to become error passive.
The analysis of such sporadic errors requires a detailed knowledge of the CAN bit
synchronization inside a CAN node and of the CAN nodes’ interaction on the CAN bus.
•
•
Software can follow the INTID in the Interrupt Register.
Software can poll the interrupt pending register, see
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
Chapter 16: LPC111x/LPC11Cxx C_CAN controller
Section
16.6.3.5.
UM10398
© NXP B.V. 2012. All rights reserved.
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