LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 391

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

23.1 How to read this chapter
23.2 Basic configuration
23.3 Features
UM10398
User manual
The WDT block (not windowed) is available for parts LPC111x and LPC11Cxx.
For parts LPC11Cxx only, a clock source lock feature is implemented whenever the WDT
is enabled.
The WDT is configured using the following registers:
1. Pins: The WDT uses no external pins.
2. Power: In the SYSAHBCLKCTRL register, set bit 15
3. Peripheral clock: Select the watchdog clock source
4. Lock features: Once the watchdog timer is enabled by setting the WDEN bit in the
•
•
•
•
•
•
•
•
UM10398
Chapter 23: LPC111x/LPC11Cxx WatchDog Timer (WDT)
Rev. 12 — 24 September 2012
peripheral clock by writing to the WDTCLKDIV register
Remark: The frequency of the watchdog oscillator is undefined after reset. The
watchdog oscillator frequency must be programmed by writing to the WDTOSCCTRL
register (see
WDMOD register, the following lock features are in effect:
a. The WDEN bit cannot be changed to 0, that is the WDT cannot be disabled
b. The watch dog clock source cannot be changed. If the WDT is needed in
Internally resets chip if not periodically reloaded.
Debug mode.
Enabled by software but requires a hardware reset or a Watchdog reset/interrupt to
be disabled.
Incorrect/Incomplete feed sequence causes reset/interrupt if enabled.
Flag to indicate Watchdog reset.
Programmable 24 bit timer with internal pre-scaler.
Selectable time period from (T
T
The Watchdog clock (WDCLK) source is selected in the syscon block from the
Internal RC oscillator (IRC), the main clock, or the Watchdog oscillator, see
This gives a wide range of potential timing choices for Watchdog operation under
different power reduction conditions. For increased reliability, it also provides the
ability to run the Watchdog timer from an entirely internal source that is not dependent
on an external crystal and its associated components and wiring.
WDCLK
(LPC111x/101/201/301 and LPC11Cxx).
Deep-sleep mode, select the watch dog oscillator as the clock source before
setting the WDEN bit. (LPC11Cxx only).
 4.
All information provided in this document is subject to legal disclaimers.
Table
Rev. 12 — 24 September 2012
13) before using the watchdog oscillator for the WDT.
WDCLK
 256  4) to (T
Table
WDCLK
(Table
(Table
25) and enable the WDT
 2
21).
27).
24
 4) in multiples of
© NXP B.V. 2012. All rights reserved.
User manual
Table
391 of 538
25.