LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 204

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
13.5.10 UART Modem Status Register
13.5.11 UART Scratch Pad Register (U0SCR - 0x4000 801C)
The U0MSR is a read-only register that provides status information on the modem input
signals. U0MSR[3:0] is cleared on U0MSR read. Note that modem signals have no direct
effect on the UART operation. They facilitate the software implementation of modem
signal operations.
Table 196. UART Modem Status Register (U0MSR - address 0x4000 8018) bit description
The U0SCR has no effect on the UART operation. This register can be written and/or read
at user’s discretion. There is no provision in the interrupt interface that would indicate to
the host that a read or write of the U0SCR has occurred.
Table 197. UART Scratch Pad Register (U0SCR - address 0x4000 801C) bit description
Bit Symbol Value Description
0
1
2
3
4
5
6
7
31:
8
Bit Symbol Description
7:0 Pad
31:
8
DCTS
DDSR
TERI
DDCD
CTS
DSR
RI
DCD
-
-
-
A readable, writable byte.
Reserved
All information provided in this document is subject to legal disclaimers.
0
1
0
1
0
1
0
1
Delta CTS. Set upon state change of input CTS. Cleared on a
U0MSR read.
No change detected on modem input CTS.
State change detected on modem input CTS.
Delta DSR. Set upon state change of input DSR. Cleared on a
U0MSR read.
No change detected on modem input DSR.
State change detected on modem input DSR.
Trailing Edge RI. Set upon low to high transition of input RI. Cleared
on a U0MSR read.
No change detected on modem input, RI.
Low-to-high transition detected on RI.
Delta DCD. Set upon state change of input DCD. Cleared on a
U0MSR read.
No change detected on modem input DCD.
State change detected on modem input DCD.
Clear To Send State. Complement of input signal CTS. This bit is
connected to U0MCR[1] in modem loopback mode.
Data Set Ready State. Complement of input signal DSR. This bit is
connected to U0MCR[0] in modem loopback mode.
Ring Indicator State. Complement of input RI. This bit is connected
to U0MCR[2] in modem loopback mode.
Data Carrier Detect State. Complement of input DCD. This bit is
connected to U0MCR[3] in modem loopback mode.
Reserved
Rev. 12 — 24 September 2012
Chapter 13: LPC111x/LPC11Cxx UART
UM10398
© NXP B.V. 2012. All rights reserved.
Reset
Value
0x00
-
204 of 538
Reset
Value
0
0
0
0
0
0
0
0
-