LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 265

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
15.10.6.2 Data transfer after loss of arbitration
15.10.6.3 Forced access to the I
Arbitration may be lost in the master transmitter and master receiver modes (see
Figure
0x78, and 0xB0 (see
If the STA flag in CON is set by the routines which service these states, then, if the bus is
free again, a START condition (state 0x08) is transmitted without intervention by the CPU,
and a retry of the total serial transfer can commence.
In some applications, it may be possible for an uncontrolled source to cause a bus
hang-up. In such situations, the problem may be caused by interference, temporary
interruption of the bus or a temporary short-circuit between SDA and SCL.
If an uncontrolled source generates a superfluous START or masks a STOP condition,
then the I
obtained within a reasonable amount of time, then a forced access to the I
possible. This is achieved by setting the STO flag while the STA flag is still set. No STOP
condition is transmitted. The I
and is able to transmit a START condition. The STO flag is cleared by hardware (see
Figure
08H
Fig 57. Simultaneous Repeated START conditions from two masters
Fig 58. Forced access to a busy I
S
51). Loss of arbitration is indicated by the following states in STAT; 0x38, 0x68,
58).
SLA
2
C-bus stays busy indefinitely. If the STA flag is set and bus access is not
STO flag
SDA line
STA flag
SCL line
W
All information provided in this document is subject to legal disclaimers.
18H
A
Rev. 12 — 24 September 2012
Figure 53
DATA
2
C-bus
2
C hardware behaves as if a STOP condition was received
time limit
and
repeated START earlier
other Master sends
28H
2
Chapter 15: LPC111x/LPC11Cxx I2C-bus controller
A
C-bus
Figure
S
54).
OTHER MASTER
CONTINUES
condition
start
retry
08H
P
UM10398
© NXP B.V. 2012. All rights reserved.
S
2
C-bus is
SLA
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