LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 505

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
28.6.3.5 System Control Register
Table 451. AIRCR bit assignments
The SCR controls features of entry to and exit from low power state. See the register
summary in
Table 452. SCR bit assignments
Bits
[31:16]
[15]
[14:3]
[2]
[1]
[0]
Bits
[31:5]
[4]
[3]
[2]
[1]
[0]
Name
-
SEVONPEND
-
SLEEPDEEP
SLEEPONEXIT Indicates sleep-on-exit when returning from Handler mode to Thread
-
Name
Read: Reserved
Write: VECTKEY
ENDIANESS
-
SYSRESETREQ
VECTCLRACTIVE
-
Table 28–448
Chapter 28: LPC111x/LPC11Cxx Appendix: ARM Cortex-M0 reference
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
for its attributes. The bit assignments are:
Function
Reserved.
Send Event on Pending bit:
0 = only enabled interrupts or events can wake-up the processor,
disabled interrupts are excluded
1 = enabled events and all interrupts, including disabled interrupts,
can wake-up the processor.
When an event or interrupt enters pending state, the event signal
wakes up the processor from WFE. If the processor is not waiting for
an event, the event is registered and affects the next WFE.
The processor also wakes up on execution of an SEV instruction.
Reserved.
Controls whether the processor uses sleep or deep sleep as its low
power mode:
0 = sleep
1 = deep sleep.
mode:
0 = do not sleep when returning to Thread mode.
1 = enter sleep, or deep sleep, on return from an ISR to Thread
mode.
Setting this bit to 1 enables an interrupt driven application to avoid
returning to an empty main application.
Reserved.
Type
RW
RO
-
WO
WO
-
Function
Register key:
Reads as Unknown
On writes, write 0x05FA to VECTKEY, otherwise the
write is ignored.
Data endianness implemented:
0 = Little-endian
1 = Big-endian.
Reserved
System reset request:
0 = no effect
1 = requests a system level reset.
This bit reads as 0.
Reserved for debug use. This bit reads as 0. When
writing to the register you must write 0 to this bit,
otherwise behavior is Unpredictable.
Reserved.
UM10398
© NXP B.V. 2012. All rights reserved.
505 of 538