LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 275

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

16.1 How to read this chapter
16.2 Basic configuration
16.3 Features
UM10398
User manual
The C_CAN block is available in LPC11Cxx parts only (LPC11C00 series).
The LPC11C22 and LPC11C24 parts include an on-chip, high-speed transceiver. For
these parts, the CAN_RXD and CAN_TXD signals are connected internally to the on-chip
transceiver, and the transceiver signals are pinned out (see
The C_CAN is configured using the following registers:
The peripheral clock to the C_CAN (the C_CAN system clock) and to the programmable
C_CAN clock divider (see
clock can be disabled through bit 17 in the SYSAHBCLKCTRL register for power savings.
Remark: If C_CAN baudrates above 100 kbit/s are required, the system oscillator must
be selected as the clock source for the system clock. For lower baudrates, the IRC may
also be used as clock source.
1. Power: In the SYSAHBCLKCTRL register, set bit 17
2. Clocking: For an accurate peripheral clock to the C_CAN block, select the system
3. Reset: Before accessing the C_CAN block, ensure that the CAN_RST_N bit (bit 3) in
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UM10398
Chapter 16: LPC111x/LPC11Cxx C_CAN controller
Rev. 12 — 24 September 2012
oscillator either as the main clock
Do not select the IRC if C_CAN baud rates above 100 kbit/s are required.
the PRESETCTRL register
C_CAN block.
Conforms to protocol version 2.0 parts A and B.
Supports bit rate of up to 1 Mbit/s.
Supports 32 Message Objects.
Each Message Object has its own identifier mask.
Provides programmable FIFO mode (concatenation of Message Objects).
Provides maskable interrupts.
Supports Disabled Automatic Retransmission (DAR) mode for time-triggered CAN
applications.
Provides programmable loop-back mode for self-test operation.
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
Table
(Table
274) is provided by the system clock
(Table
9) is set to 1. This de-asserts the reset signal to the
18) or as input to the system PLL
(Table
Table
21).
243).
(seeTable
© NXP B.V. 2012. All rights reserved.
User manual
(Table
21). This
275 of 538
16).