LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 3

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

1.1 Introduction
UM10398
User manual
The LPC111x/LPC11Cxx are a ARM Cortex-M0 based, low-cost 32-bit MCU family,
designed for 8/16-bit microcontroller applications, offering performance, low power, simple
instruction set and memory addressing together with reduced code size compared to
existing 8/16-bit architectures.
The LPC111x/LPC11Cxx operate at CPU frequencies of up to 50 MHz.
The peripheral complement of the LPC111x/LPC11Cxx includes up to 32 kB of flash
memory, up to 8 kB of data memory, one C_CAN controller (LPC11Cxx), one Fast-mode
Plus I
features, four general purpose timers, a 10-bit ADC, and up to 42 general purpose I/O
pins.
On-chip C_CAN drivers and flash In-System Programming tools via C_CAN are included
on the LPC11Cxx. In addition, parts LPC11C2x are equipped with an on-chip CAN
transceiver.
Remark: This user manual covers the LPC111x/LPC11Cxx parts and the LPC11D14
dual-chip part with PCF8576D LCD controller. The LPC111x/LPC11Cxx parts are grouped
by the following series and part names (see
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UM10398
Chapter 1: LPC111x/LPC11Cxx Introductory information
Rev. 12 — 24 September 2012
LPC1100 series (parts LPC111x/101/201/301)
LPC1100L series (parts LPC111x/102/202/302) and part LPC11D14 with LCD
controller.
LPC1100XL series (parts LPC111x/103/203/323/333)
LPC11C00 series (parts LPC11C1x/301 and LPC11C2x/301) with C_CAN controller.
2
C-bus interface, one RS-485/EIA-485 UART, up to two SPI interfaces with SSP
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
Table 1
for a feature overview):
© NXP B.V. 2012. All rights reserved.
User manual
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