LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 186

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
12.3.4 GPIO interrupt both edges sense register
12.3.5 GPIO interrupt event register
12.3.6 GPIO interrupt mask register
12.3.7 GPIO raw interrupt status register
Table 176. GPIOnIBE register (GPIO0IBE, address 0x5000 8008 to GPIO3IBE, address 0x5003
Table 177. GPIOnIEV register (GPIO0IEV, address 0x5000 800C to GPIO3IEV, address 0x5003
Bits set to HIGH in the GPIOnIE register allow the corresponding pins to trigger their
individual interrupts and the combined GPIOnINTR line. Clearing a bit disables interrupt
triggering on that pin.
Table 178. GPIOnIE register (GPIO0IE, address 0x5000 8010 to GPIO3IE, address 0x5003
Bits read HIGH in the GPIOnRIS register reflect the raw (prior to masking) interrupt status
of the corresponding pins indicating that all the requirements have been met before they
are allowed to trigger the GPIOIE. Bits read as zero indicate that the corresponding input
pins have not initiated an interrupt. The register is read-only.
Bit
11:0
31:12
Bit
11:0
31:12
Bit
11:0
31:12
Symbol Description
IBE
-
Symbol
IEV
-
Symbol Description
MASK
-
8008) bit description
800C) bit description
8010) bit description
All information provided in this document is subject to legal disclaimers.
Selects interrupt on pin x to be triggered on both edges (x = 0
to 11).
0 = Interrupt on pin PIOn_x is controlled through register
GPIOnIEV.
1 = Both edges on pin PIOn_x trigger an interrupt.
Reserved
Selects interrupt on pin x to be masked (x = 0 to 11).
0 = Interrupt on pin PIOn_x is masked.
1 = Interrupt on pin PIOn_x is not masked.
Reserved
Description
Selects interrupt on pin x to be triggered rising or falling
edges (x = 0 to 11).
0 = Depending on setting in register GPIOnIS (see
Table
trigger an interrupt.
1 = Depending on setting in register GPIOnIS (see
Table
trigger an interrupt.
Reserved
Rev. 12 — 24 September 2012
175), falling edges or LOW level on pin PIOn_x
175), rising edges or HIGH level on pin PIOn_x
Chapter 12: LPC111x/LPC11Cxx General Purpose I/O (GPIO)
UM10398
© NXP B.V. 2012. All rights reserved.
Reset
value
0x00
-
Reset
value
0x00
-
Reset
value
0x00
-
Access
R/W
-
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Access
R/W
-
Access
R/W
-