LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 479

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
28.5.5.1.1 Syntax
28.5.5.1.2 Operation
28.5.5.1 ADC, ADD, RSB, SBC, and SUB
Add with carry, Add, Reverse Subtract, Subtract with carry, and Subtract.
ADCS {Rd,} Rn, Rm
ADD{S} {Rd,} Rn, <Rm|#imm>
RSBS {Rd,} Rn, Rm, #0
SBCS {Rd,} Rn, Rm
SUB{S} {Rd,} Rn,
<Rm|#imm>
Where:
When the optional Rd register specifier is omitted, it is assumed to take the same value as
Rn, for example ADDS R1,R2 is identical to ADDS R1,R1,R2.
The ADCS instruction adds the value in Rn to the value in Rm, adding a further one if the
carry flag is set, places the result in the register specified by Rd and updates the N, Z, C,
and V flags.
The ADD instruction adds the value in Rn to the value in Rm or an immediate value
specified by imm and places the result in the register specified by Rd.
The ADDS instruction performs the same operation as ADD and also updates the N, Z, C
and V flags.
The RSBS instruction subtracts the value in Rn from zero, producing the arithmetic
negative of the value, and places the result in the register specified by Rd and updates the
N, Z, C and V flags.
The SBCS instruction subtracts the value of Rm from the value in Rn, deducts a further
one if the carry flag is set. It places the result in the register specified by Rd and updates
the N, Z, C and V flags.
The SUB instruction subtracts the value in Rm or the immediate specified by imm. It
places the result in the register specified by Rd.
The SUBS instruction performs the same operation as SUB and also updates the N, Z, C
and V flags.
Use ADC and SBC to synthesize multiword arithmetic, see
S causes an ADD or SUB instruction to update flags
Rd specifies the result register
Rn specifies the first source register
Rm specifies the second source register
imm specifies a constant immediate value.
Chapter 28: LPC111x/LPC11Cxx Appendix: ARM Cortex-M0 reference
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
Section
28.5.5.1.4.
UM10398
© NXP B.V. 2012. All rights reserved.
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