LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 525

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
Fig 81. A timer cycle in which PR=2, MRx=6, and both
Fig 82. Sample PWM waveforms with a PWM cycle length
Fig 83. 32-bit counter/timer block diagram. . . . . . . . . . .382
Fig 84. Windowed Watchdog Timer (WWDT) block
Fig 85. Early Watchdog Feed with Windowed Mode
Fig 86. Correct Watchdog Feed with Windowed Mode
Fig 87. Watchdog Warning Interrupt . . . . . . . . . . . . . . .390
Fig 88. Watchdog block diagram . . . . . . . . . . . . . . . . . .395
Fig 89. System tick timer block diagram . . . . . . . . . . . .396
Fig 90. Boot process flowchart . . . . . . . . . . . . . . . . . . .410
Fig 91. IAP parameter passing . . . . . . . . . . . . . . . . . . .431
Fig 92. Algorithm for generating a 128-bit signature . . .441
Fig 93. Connecting the SWD pins to a standard SWD
Fig 94. Cortex-M0 implementation. . . . . . . . . . . . . . . . .444
Fig 95. Processor core register set . . . . . . . . . . . . . . . .447
Fig 96. APSR, IPSR, EPSR register bit assignments . .448
Fig 97. Generic ARM Cortex-M0 memory map . . . . . . .453
Fig 98. Memory ordering restrictions . . . . . . . . . . . . . . .454
Fig 99. Little-endian format . . . . . . . . . . . . . . . . . . . . . .456
Fig 100. Vector table . . . . . . . . . . . . . . . . . . . . . . . . . . . .459
Fig 101. Exception entry stack contents . . . . . . . . . . . . .461
Fig 102. ASR #3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .468
Fig 103. LSR #3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .469
Fig 104. LSL #3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .469
Fig 105. ROR #3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .470
Fig 106. IPR register . . . . . . . . . . . . . . . . . . . . . . . . . . . .499
UM10398
User manual
interrupt and reset on match are enabled . . . . .380
interrupt and stop on match are enabled . . . . . .381
of 100 (selected by MR3) and MAT3:0 enabled as
PWM outputs by the PWMC register. . . . . . . . .381
diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .385
Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .389
Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .390
connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .443
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
Chapter 29: Supplementary information
UM10398
© NXP B.V. 2012. All rights reserved.
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