LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 286

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
Table 253. Structure of a message object in the message RAM
UM10398
User manual
UMASK
IF1/2_MCTRL
RMTEN
IF1/2_MCTRL
DATA0
IF1/2_DA1
16.6.2.1 Message objects
16.6.2.2 CAN message interface command request registers
TXRQST
DATA1
MSK[28:0]
Table 252. Message interface registers
There are 32 Message Objects in the Message RAM. To avoid conflicts between CPU
access to the Message RAM and CAN message reception and transmission, the CPU
cannot directly access the Message Objects. The message objects are accessed through
the IFx Interface Registers.
For details of message handling, see
A message object contains the information from the various bits in the message interface
registers.
message object. The bits of a message object and the respective interface register where
this bit is set or cleared are shown. For bit functions see the corresponding interface
register.
A message transfer is started as soon as the CPU has written the message number to the
Command Request Register. With this write operation the BUSY bit is automatically set to
‘1’ and the signal CAN_WAIT_B is pulled LOW to notify the CPU that a transfer is in
progress. After a wait time of 3 to 6 CAN_CLK periods, the transfer between the Interface
Register and the Message RAM has completed. The BUSY bit is set back to zero and the
signal CAN_WAIT_B is set back.
IF1 register names
CANIF1_CMDREQ
CANIF1_CMDMASK
CANIF1_MASK1
CANIF1_MASK2
CANIF1_ARB1
CANIF1_ARB2
CANIF1_MCTRL
CANIF1_DA1
CANIF1_DA2
CANIF1_DB1
CANIF1_DB2
MSGVAL
IF1/2_MSK1/2
DATA2
MXTD
IF1/2_DA2
Table 253
ID[28:0]
MDIR
DATA3
All information provided in this document is subject to legal disclaimers.
IF1/2_ARB1/2
below shows a schematic representation of the structure of the
Rev. 12 — 24 September 2012
IF1 register set
IF1 command request
IF1 command mask
IF1 mask 1
IF1 mask 2
IF1 arbitration 1
IF1 arbitration 2
IF1 message control
IF1 data A1
IF1 data A2
IF1 data B1
IF1 data B2
XTD
EOB
DATA4
DIR
IF1/2_DB1
Chapter 16: LPC111x/LPC11Cxx C_CAN controller
NEWDAT
Section
DATA5
DLC3
16.7.3.
IF2 register names
CANIF2_CMDREQ
CANIF2_CMDMASK
CANIF2_MSK1
CANIF2_MSK2
CANIF2_ARB1
CANIF2_ARB2
CANIF2_MCTRL
CANIF2_DA1
CANIF2_DA2
CANIF2_DB1
CANIF2_DB2
MSGLST
IF1/2_MCTRL
DATA6
DLC2
RXIE
IF1/2_MCTRL
DATA7
IF1/2_DB2
IF2 register set
IF2 command request
IF2 command mask
IF2 mask 1
IF2 mask 2
IF2 arbitration 1
IF2 arbitration 2
IF2 message control
IF2 data A1
IF2 data A2
IF2 data B1
IF2 data B2
DLC1
UM10398
TXIE
© NXP B.V. 2012. All rights reserved.
INTPND
DLC0
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