LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 473

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
28.5.4.1.2 Operation
28.5.4.1.3 Restrictions
28.5.4.1.4 Condition flags
28.5.4.1.5 Examples
28.5.4.2.1 Syntax
28.5.4.2.2 Operation
28.5.4.2 LDR and STR, immediate offset
where:
ADR generates an address by adding an immediate value to the PC, and writes the result
to the destination register.
ADR facilitates the generation of position-independent code, because the address is
PC-relative.
If you use ADR to generate a target address for a BX or BLX instruction, you must ensure
that bit[0] of the address you generate is set to 1 for correct execution.
In this instruction Rd must specify R0-R7. The data-value addressed must be word
aligned and within 1020 bytes of the current PC.
This instruction does not change the flags.
Load and Store with immediate offset.
LDR Rt, [<Rn | SP> {, #imm}]
LDR<B|H> Rt, [Rn {, #imm}]
STR Rt, [<Rn | SP>, {,#imm}]
STR<B|H> Rt, [Rn {,#imm}]
where:
LDR, LDRB and LDRH instructions load the register specified by Rt with either a word,
byte or halfword data value from memory. Sizes less than word are zero extended to
32-bits before being written to the register specified by Rt.
Rd is the destination register.
label is a PC-relative expression. See
ADR R1, TextMessage ; Write address value of a location labelled as
ADR R3, [PC,#996]
Rt is the register to load or store.
Rn is the register on which the memory address is based.
imm is an offset from Rn. If imm is omitted, it is assumed to be zero.
Chapter 28: LPC111x/LPC11Cxx Appendix: ARM Cortex-M0 reference
All information provided in this document is subject to legal disclaimers.
; TextMessage to R1
Rev. 12 — 24 September 2012
; Set R3 to value of PC + 996.
Section
28–28.5.3.5.
UM10398
© NXP B.V. 2012. All rights reserved.
473 of 538