LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 358

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
20.7.3 Timer Counter (TMR32B0TC - address 0x4001 4008 and
20.7.4 Prescale Register (TMR32B0PR - address 0x4001 400C and
20.7.5 Prescale Counter Register (TMR32B0PC - address 0x4001 4010 and
Table 314: Timer Control Register (TMR32B0TCR - address 0x4001 4004 and TMR32B1TCR -
TMR32B1TC - address 0x4001 8008)
The 32-bit Timer Counter is incremented when the Prescale Counter reaches its terminal
count. Unless it is reset before reaching its upper limit, the TC will count up through the
value 0xFFFF FFFF and then wrap back to the value 0x0000 0000. This event does not
cause an interrupt, but a Match register can be used to detect an overflow if needed.
Table 315: Timer counter registers (TMR32B0TC, address 0x4001 4008 and TMR32B1TC
TMR32B1PR - address 0x4001 800C)
The 32-bit Prescale Register specifies the maximum value for the Prescale Counter.
Table 316: Prescale registers (TMR32B0PR, address 0x4001 400C and TMR32B1PR
TMR32B1PC - address 0x4001 8010)
The 32-bit Prescale Counter controls division of PCLK by some constant value before it is
applied to the Timer Counter. This allows control of the relationship between the resolution
of the timer and the maximum time before the timer overflows. The Prescale Counter is
incremented on every PCLK. When it reaches the value stored in the Prescale Register,
the Timer Counter is incremented, and the Prescale Counter is reset on the next PCLK.
This causes the TC to increment on every PCLK when PR = 0, every 2 PCLKs when
PR = 1, etc.
Bit
0
1
31:2
Bit
31:0
Bit
31:0
Symbol
CEn
CRst
-
Symbol
Symbol
TC
PR
address 0x4001 8004) bit description
0x4001 8008) bit description
0x4001 800C) bit description
Chapter 20: LPC1100/LPC1100C/LPC1100L series: 32-bit counter/timer
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
Description
Timer counter value.
Description
Prescale value.
Description
When one, the Timer Counter and Prescale Counter are
enabled for counting. When zero, the counters are
disabled.
When one, the Timer Counter and the Prescale Counter
are synchronously reset on the next positive edge of
PCLK. The counters remain reset until TCR[1] is
returned to zero.
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
UM10398
© NXP B.V. 2012. All rights reserved.
Reset value
0
0
NA
358 of 538
Reset
value
0
Reset
value
0