LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 203

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
Table 195. UART Line Status Register (U0LSR - address 0x4000 8014, Read Only) bit
Bit Symbol
3
4
5
6
7
31:
8
FE
BI
THRE
TEMT
RXFE
-
description
All information provided in this document is subject to legal disclaimers.
Value
-
0
1
0
1
0
1
0
1
0
1
Rev. 12 — 24 September 2012
…continued
Description
Framing Error. When the stop bit of a received character is a
logic 0, a framing error occurs. A U0LSR read clears
U0LSR[3]. The time of the framing error detection is
dependent on U0FCR0. Upon detection of a framing error, the
RX will attempt to re-synchronize to the data and assume that
the bad stop bit is actually an early start bit. However, it cannot
be assumed that the next received byte will be correct even if
there is no Framing Error.
Note: A framing error is associated with the character at the
top of the UART RBR FIFO.
Framing error status is inactive.
Framing error status is active.
Break Interrupt. When RXD1 is held in the spacing state (all
zeros) for one full character transmission (start, data, parity,
stop), a break interrupt occurs. Once the break condition has
been detected, the receiver goes idle until RXD1 goes to
marking state (all ones). A U0LSR read clears this status bit.
The time of break detection is dependent on U0FCR[0].
Note: The break interrupt is associated with the character at
the top of the UART RBR FIFO.
Break interrupt status is inactive.
Break interrupt status is active.
Transmitter Holding Register Empty. THRE is set immediately
upon detection of an empty UART THR and is cleared on a
U0THR write.
U0THR contains valid data.
U0THR is empty.
Transmitter Empty. TEMT is set when both U0THR and
U0TSR are empty; TEMT is cleared when either the U0TSR or
the U0THR contain valid data. This bit is updated as soon as
50 % of the first stop bit has been transmitted or a byte has
been written into the THR.
U0THR and/or the U0TSR contains valid data.
U0THR and the U0TSR are empty.
Error in RX FIFO. U0LSR[7] is set when a character with a RX
error such as framing error, parity error or break interrupt, is
loaded into the U0RBR. This bit is cleared when the U0LSR
register is read and there are no subsequent errors in the
UART FIFO.
U0RBR contains no UART RX errors or U0FCR[0]=0.
UART RBR contains at least one UART RX error.
Reserved
Chapter 13: LPC111x/LPC11Cxx UART
UM10398
© NXP B.V. 2012. All rights reserved.
203 of 538
Reset
Value
0
0
1
1
0
-