LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 487

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
28.5.5.8.5 Examples
28.5.5.9.1 Syntax
28.5.5.9.2 Operation
28.5.5.9.3 Restrictions
28.5.5.9.4 Condition flags
28.5.5.9.5 Examples
28.5.5.9 TST
28.5.6 Branch and control instructions
Test bits.
TST Rn, Rm
where:
This instruction tests the value in a register against another register. It updates the
condition flags based on the result, but does not write the result to a register.
The TST instruction performs a bitwise AND operation on the value in Rn and the value in
Rm. This is the same as the ANDS instruction, except that it discards the result.
To test whether a bit of Rn is 0 or 1, use the TST instruction with a register that has that bit
set to 1 and all other bits cleared to 0.
In these instructions, Rn and Rm must only specify R0-R7.
This instruction:
Table 436
Table 436. Branch and control instructions
Mnemonic
B{cc}
•
•
SXTH R4, R6
Rn is the register holding the first operand.
Rm the register to test against.
TST
updates the N and Z flags according to the result
does not affect the C or V flags.
UXTB R3, R1
R0, R1 ; Perform bitwise AND of R0 value and R1 value,
shows the branch and control instructions:
Chapter 28: LPC111x/LPC11Cxx Appendix: ARM Cortex-M0 reference
All information provided in this document is subject to legal disclaimers.
; condition code flags are updated but result is discarded
; Obtain the lower halfword of the
Brief description
Branch {conditionally}
; value in R6 and then sign extend to
; 32 bits and write the result to R4.
; extend it, and write the result to R3
Rev. 12 — 24 September 2012
; Extract lowest byte of the value in R10 and zero
See
Section 28–28.5.6.1
UM10398
© NXP B.V. 2012. All rights reserved.
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