LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 183

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

12.1 How to read this chapter
Table 171. GPIO configuration
12.2 Introduction
UM10398
User manual
Part
LPC1110
LPC1111
LPC1112
LPC1113
LPC1114
LPC11D14 LQFP100
LPC11C12 LQFP48
LPC11C14 LQFP48
LPC11C22 LQFP48
LPC11C24 LQFP48
Package
SO20/
TSSOP20
HVQFN33 PIO0_0 to PIO0_11 PIO1_0 to PIO1_11 PIO2_0
TSSOP20
TSSOP28
HVQFN33 PIO0_0 to PIO0_11 PIO1_0 to PIO1_11 PIO2_0
HVQFN33 PIO0_0 to PIO0_3;
HVQFN33 PIO0_0 to PIO0_11 PIO1_0 to PIO1_11 PIO2_0
LQFP48
TSSOP28
HVQFN33 PIO0_0 to PIO0_11 PIO1_0 to PIO1_11 PIO2_0
LQFP48
12.2.1 Features
The number of GPIO pins available on each port depends on the LPC111x/LPC11Cxx part
and the package. See
Register bits corresponding to PIOn_m pins which are not available are reserved.
PIO0_0 to PIO0_11 PIO1_0 to PIO1_9
GPIO port 0
PIO0_0 to PIO0_2;
PIO0_4 to PIO0_6;
PIO0_8 to PIO0_11
PIO0_0 to PIO0_3;
PIO0_8 to PIO0_11
PIO0_0 to PIO0_11 PIO1_0 to PIO1_9
PIO0_4 to PIO0_11
PIO0_0 to PIO0_11 PIO1_0 to PIO1_11 PIO2_0 to PIO2_11 PIO3_0 to PIO3_5
PIO0_0 to PIO0_11 PIO1_0 to PIO1_11 PIO2_0 to PIO2_11 PIO3_0 to PIO3_5
PIO0_0 to PIO0_11 PIO1_0 to PIO1_11 PIO2_0 to PIO2_11 PIO3_0 to PIO3_5
PIO0_0 to PIO0_11 PIO1_0 to PIO1_11 PIO2_0 to PIO2_11 PIO3_0 to PIO3_3
PIO0_0 to PIO0_11 PIO1_0 to PIO1_11 PIO2_0 to PIO2_11 PIO3_0 to PIO3_3
PIO0_0 to PIO0_11 PIO1_0 to PIO1_11
PIO0_0 to PIO0_11 PIO1_0 to PIO1_11
•
•
•
•
UM10398
Chapter 12: LPC111x/LPC11Cxx General Purpose I/O (GPIO)
Rev. 12 — 24 September 2012
GPIO pins can be configured as input or output by software.
Each individual port pin can serve as an edge or level-sensitive interrupt request.
Interrupts can be configured on single falling or rising edges and on both edges.
Level-sensitive interrupt pins can be HIGH or LOW-active.
All information provided in this document is subject to legal disclaimers.
GPIO port 1
PIO1_0 to PIO1_3;
PIO1_6 to PIO1_7
PIO1_0 to PIO1_3;
PIO1_6 to PIO1_7
PIO1_0 to PIO1_4;
PIO1_6 to PIO1_8
except PIO1_9
except PIO1_9
Rev. 12 — 24 September 2012
Table 171
for available GPIO pins:
GPIO port 2
-
-
-
-
-
PIO2_0 to PIO2_11
except PIO2_4,
PIO2_5, PIO2_9
PIO2_0 to PIO2_11
except PIO2_4,
PIO2_5, PIO2_9
GPIO port 3
-
PIO3_2; PIO3_4; PIO3_5 28
-
-
PIO3_2; PIO3_4; PIO3_5 28
-
-
PIO3_2; PIO3_4; PIO3_5 28
PIO3_0 to PIO3_3
PIO3_0 to PIO3_3
PIO3_2; PIO3_4; PIO3_5 28
© NXP B.V. 2012. All rights reserved.
User manual
183 of 538
42
42
42
40
40
Total
GPIO
pins
16
14
22
22
36
36