LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 477

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
28.5.4.5.4 Condition flags
28.5.4.5.5 Examples
28.5.4.5.6 Incorrect examples
28.5.4.6.1 Syntax
28.5.4.6.2 Operation
28.5.4.6.3 Restrictions
28.5.4.6 PUSH and POP
These instructions do not change the flags.
Push registers onto, and pop registers off a full-descending stack.
PUSH reglist
POP reglist
where:
PUSH stores registers on the stack, with the lowest numbered register using the lowest
memory address and the highest numbered register using the highest memory address.
POP loads registers from the stack, with the lowest numbered register using the lowest
memory address and the highest numbered register using the highest memory address.
PUSH uses the value in the SP register minus four as the highest memory address,
POP uses the value in the SP register as the lowest memory address, implementing a
full-descending stack. On completion,
PUSH updates the SP register to point to the location of the lowest store value,
POP updates the SP register to point to the location above the highest location loaded.
If a POP instruction includes PC in its reglist, a branch to this location is performed when
the POP instruction has completed. Bit[0] of the value read for the PC is used to update
the APSR T-bit. This bit must be 1 to ensure correct operation.
In these instructions:
•
•
•
LDM
STM
reglist is a non-empty list of registers, enclosed in braces. It can contain register ranges.
It must be comma separated if it contains more than one register or register range.
the value in the register specified by Rn must be word aligned. See
Section 28–28.5.3.4
for STM, if Rn appears in reglist, then it must be the first register in the list.
reglist must use only R0-R7.
STMIA R1!,{R2-R4,R6}
LDM
R5!,{R4,R5,R6} ; Value stored for R5 is unpredictable
R0,{R0,R3,R4}
R2,{}
Chapter 28: LPC111x/LPC11Cxx Appendix: ARM Cortex-M0 reference
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
; LDMIA is a synonym for LDM
; There must be at least one register in the list
for more information.
UM10398
© NXP B.V. 2012. All rights reserved.
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