LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 326

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
18.4 Applications
18.5 Description
18.6 Pin description
Table 278. Counter/timer pin description
18.7 Register description
UM10398
User manual
Pin
CT16B0_CAP0
CT16B1_CAP0
CT16B0_MAT[2:0]
CT16B1_MAT[1:0]
Each Counter/timer is designed to count cycles of the peripheral clock (PCLK) or an
externally supplied clock and can optionally generate interrupts or perform other actions at
specified timer values based on four match registers. The peripheral clock is provided by
the system clock (see
trap the timer value when an input signal transitions, optionally generating an interrupt.
In PWM mode, three match registers on CT16B0 and two match registers on CT16B1 can
be used to provide a single-edge controlled PWM output on the match output pins. It is
recommended to use the match registers that are not pinned out to control the PWM cycle
length.
Remark: The 16-bit counter/timer0 (CT16B0) and the 16-bit counter/timer1 (CT16B1) are
functionally identical except for the peripheral base address.
Table 278
The 16-bit counter/timer0 contains the registers shown in
counter/timer1 contains the registers shown in
follow.
Type
Input
Output
•
•
•
•
Interval timer for counting internal events
Pulse Width Demodulator via capture input
Free-running timer
Pulse Width Modulator via match outputs
gives a brief summary of each of the counter/timer related pins.
Description
Capture Signal:
A transition on a capture pin can be configured to load the Capture Register with the
value in the counter/timer and optionally generate an interrupt.
Counter/Timer block can select a capture signal as a clock source instead of the PCLK
derived clock. For more details see
External Match Outputs of CT16B0/1:
When a match register of CT16B0/1 (MR3:0) equals the timer counter (TC), this output
can either toggle, go LOW, go HIGH, or do nothing. The External Match Register
(EMR) and the PWM Control Register (PWMCON) control the functionality of this
output.
Chapter 18: LPC1100/LPC1100C/LPC1100L series: 16-bit counter/timer
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
Figure
8). Each counter/timer also includes one capture input to
Section
Table
18.7.11.
280. More detailed descriptions
Table 279
and the 16-bit
UM10398
© NXP B.V. 2012. All rights reserved.
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