LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 208

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
13.5.15 UART Fractional Divider Register (U0FDR - 0x4000 8028)
The UART Fractional Divider Register (U0FDR) controls the clock pre-scaler for the baud
rate generation and can be read and written at the user’s discretion. This pre-scaler takes
the APB clock and generates an output clock according to the specified fractional
requirements.
Important: If the fractional divider is active (DIVADDVAL > 0) and DLM = 0, the value of
the DLL register must be 3 or greater.
Table 199. UART Fractional Divider Register (U0FDR - address 0x4000 8028) bit description
This register controls the clock pre-scaler for the baud rate generation. The reset value of
the register keeps the fractional capabilities of UART disabled making sure that UART is
fully software and hardware compatible with UARTs not equipped with this feature.
The UART baud rate can be calculated as:
Where UART_PCLK is the peripheral clock, U0DLM and U0DLL are the standard UART
baud rate divider registers, and DIVADDVAL and MULVAL are UART fractional baud rate
generator specific parameters.
The value of MULVAL and DIVADDVAL should comply to the following conditions:
The value of the U0FDR should not be modified while transmitting/receiving data or data
may be lost or corrupted.
If the U0FDR register value does not comply to these two requests, then the fractional
divider output is undefined. If DIVADDVAL is zero then the fractional divider is disabled,
and the clock will not be divided.
Bit
3:0
7:4
31:8
1. 1 MULVAL  15
2. 0  DIVADDVAL  14
3. DIVADDVAL< MULVAL
Function
DIVADDVAL
MULVAL
-
UART
All information provided in this document is subject to legal disclaimers.
baudrate
Description
Baud rate generation pre-scaler divisor value. If this field is 0,
fractional baud rate generator will not impact the UART baud rate.
Baud rate pre-scaler multiplier value. This field must be greater or
equal 1 for UART to operate properly, regardless of whether the
fractional baud rate generator is used or not.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Rev. 12 — 24 September 2012
=
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16


256

U0DLM
+
Chapter 13: LPC111x/LPC11Cxx UART
PCLK
U0DLL




1
+
DivAddVal
---------------------------- -
MulVal
UM10398
© NXP B.V. 2012. All rights reserved.


Reset
value
0
1
0
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