LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 235

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
Table 218. Register overview: I
[1]
UM10398
User manual
Name
I2C0ADR3
I2C0DATA_
BUFFER
I2C0MASK0
I2C0MASK1
I2C0MASK2
I2C0MASK3
Reset value reflects the data stored in used bits only. It does not include reserved bits content.
15.7.1 I
Access Address
R/W
RO
R/W
R/W
R/W
R/W
The CONSET registers control setting of bits in the CON register that controls operation of
the I
I
Table 219. I
I2EN I
cleared by writing 1 to the I2ENC bit in the CONCLR register. When I2EN is 0, the I
interface is disabled.
When I2EN is “0”, the SDA and SCL input signals are ignored, the I
addressed” slave state, and the STO bit is forced to “0”.
Bit
1:0
2
3
4
5
6
31:7 -
2
2
offset
0x028
0x02C
0x030
0x034
0x038
0x03C
C control register to be set. Writing a zero has no effect.
C Control Set register (I2C0CONSET - 0x4000 0000)
2
C interface. Writing a one to a bit of this register causes the corresponding bit in the
Symbol
-
AA
SI
STO
STA
I2EN
2
C Interface Enable. When I2EN is 1, the I
2
C (base address 0x4000 0000)
2
C Control Set register (I2C0CONSET - address 0x4000 0000) bit description
Description
I2C Slave Address Register 3. Contains the 7-bit slave address for
operation of the I
mode. The least significant bit determines whether a slave responds to
the General Call address.
Data buffer register. The contents of the 8 MSBs of the I2DAT shift
register will be transferred to the DATA_BUFFER automatically after
every nine bits (8 bits of data plus ACK or NACK) has been received on
the bus.
I2C Slave address mask register 0. This mask register is associated
with I2ADR0 to determine an address match. The mask register has no
effect when comparing to the General Call address (‘0000000’).
I2C Slave address mask register 1. This mask register is associated
with I2ADR1 to determine an address match. The mask register has no
effect when comparing to the General Call address (‘0000000’).
I2C Slave address mask register 2. This mask register is associated
with I2ADR2 to determine an address match. The mask register has no
effect when comparing to the General Call address (‘0000000’).
I2C Slave address mask register 3. This mask register is associated
with I2ADR3 to determine an address match. The mask register has no
effect when comparing to the General Call address (‘0000000’).
All information provided in this document is subject to legal disclaimers.
Description
Reserved. User software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Assert acknowledge flag.
I
STOP flag.
START flag.
I
Reserved. The value read from a reserved bit is not defined.
2
2
C interrupt flag.
C interface enable.
Rev. 12 — 24 September 2012
2
C interface in slave mode, and is not used in master
Chapter 15: LPC111x/LPC11Cxx I2C-bus controller
…continued
2
C interface is enabled. I2EN can be
2
C block is in the “not
UM10398
© NXP B.V. 2012. All rights reserved.
Reset
value
NA
0
0
0
0
-
235 of 538
Reset
value
0x00
0x00
0x00
0x00
0x00
0x00
2
C
[1]