LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 374

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
Table 334: Match Control Register (TMR32B0MCR - address 0x4001 4014 and TMR32B1MCR - address 0x4001 8014)
UM10398
User manual
Bit
3
4
5
6
7
8
9
10
11
31:12
Symbol Value Description
MR1I
MR1R
MR1S
MR2I
MR2R
MR2S
MR3I
MR3R
MR3S
-
bit description
21.7.7 Match Registers (TMR32B0MR0/1/2/3 - addresses 0x4001
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
4018/1C/20/24 and TMR32B1MR0/1/2/3 addresses 0x4001
8018/1C/20/24)
The Match register values are continuously compared to the Timer Counter value. When
the two values are equal, actions can be triggered automatically. The action possibilities
are to generate an interrupt, reset the Timer Counter, or stop the timer. Actions are
controlled by the settings in the MCR register.
Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.
Enabled
Disabled
Reset on MR1: the TC will be reset if MR1 matches it.
Enabled
Disabled
Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches
the TC.
Enabled
Disabled
Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC.
Enabled
Disabled
Reset on MR2: the TC will be reset if MR2 matches it.
Enabled
Disabled
Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches
the TC.
Enabled
Disabled
Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC.
Enabled
Disabled
Reset on MR3: the TC will be reset if MR3 matches it.
Enabled
Disabled
Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches
the TC.
Enabled
Disabled
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
Chapter 21: LPC1100XL series: 32-bit counter/timer CT32B0/1
UM10398
© NXP B.V. 2012. All rights reserved.
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0
0
0
0
Reset
value
0
0
0
0
0
NA