LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 466

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
Table 429. Cortex-M0 instructions
UM10398
User manual
Mnemonic
NOP
ORRS
POP
PUSH
REV
REV16
REVSH
RORS
RSBS
SBCS
SEV
STM
STR
STRB
STRH
SUB{S}
SVC
SXTB
SXTH
TST
UXTB
UXTH
WFE
WFI
28.5.2 Intrinsic functions
Operands
-
{Rd,} Rn, Rm
reglist
reglist
Rd, Rm
Rd, Rm
Rd, Rm
{Rd,} Rn, Rs
{Rd,} Rn, #0
{Rd,} Rn, Rm
-
Rn!, reglist
Rt, [Rn, <Rm|#imm>]
Rt, [Rn, <Rm|#imm>]
Rt, [Rn, <Rm|#imm>]
{Rd,} Rn, <Rm|#imm>
#imm
Rd, Rm
Rd, Rm
Rn, Rm
Rd, Rm
Rd, Rm
-
-
ISO/IEC C code cannot directly access some Cortex-M0 instructions. This section
describes intrinsic functions that can generate these instructions, provided by the CMSIS
and that might be provided by a C compiler. If a C compiler does not support an
appropriate intrinsic function, you might have to use inline assembler to access the
relevant instruction.
The CMSIS provides the following intrinsic functions to generate instructions that ISO/IEC
C code cannot directly access:
Table 430. CMSIS intrinsic functions to generate some Cortex-M0 instructions
Instruction
CPSIE i
CPSID i
ISB
DSB
DMB
NOP
Chapter 28: LPC111x/LPC11Cxx Appendix: ARM Cortex-M0 reference
All information provided in this document is subject to legal disclaimers.
Brief description
No Operation
Logical OR
Pop registers from stack
Push registers onto stack
Byte-Reverse word
Byte-Reverse packed halfwords
Byte-Reverse signed halfword
Rotate Right
Reverse Subtract
Subtract with Carry
Send Event
Store Multiple registers, increment after
Store Register as word
Store Register as byte
Store Register as halfword
Subtract
Supervisor Call
Sign extend byte
Sign extend halfword
Logical AND based test
Zero extend a byte
Zero extend a halfword
Wait For Event
Wait For Interrupt
Rev. 12 — 24 September 2012
CMSIS intrinsic function
void __enable_irq(void)
void __disable_irq(void)
void __ISB(void)
void __DSB(void)
void __DMB(void)
void __NOP(void)
Flags
-
N,Z
-
-
-
-
-
N,Z,C
N,Z,C,V
N,Z,C,V
-
-
-
-
-
N,Z,C,V
-
-
-
N,Z
-
-
-
-
Reference
Section 28–28.5.7.8
Section 28–28.5.5.2
Section 28–28.5.4.6
Section 28–28.5.4.6
Section 28–28.5.5.7
Section 28–28.5.5.7
Section 28–28.5.5.7
Section 28–28.5.5.3
Section 28–28.5.5.1
Section 28–28.5.5.1
Section 28–28.5.7.9
Section 28–28.5.4.5
Section 28–28.5.4
Section 28–28.5.4
Section 28–28.5.4
Section 28–28.5.5.1
Section 28–28.5.7.10
Section 28–28.5.5.8
Section 28–28.5.5.8
Section 28–28.5.5.9
Section 28–28.5.5.8
Section 28–28.5.5.8
Section 28–28.5.7.11
Section 28–28.5.7.12
UM10398
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