LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 248

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
15.9.7 Serial clock generator
The synchronization logic will synchronize the serial clock generator with the clock pulses
on the SCL line from another device. If two or more master devices generate clock pulses,
the “mark” duration is determined by the device that generates the shortest “marks,” and
the “space” duration is determined by the device that generates the longest “spaces”.
Figure 52
A slave may stretch the space duration to slow down the bus master. The space duration
may also be stretched for handshaking purposes. This can be done after each bit or after
a complete byte transfer. the I
been transmitted or received and the acknowledge bit has been transferred. The serial
interrupt flag (SI) is set, and the stretching continues until the serial interrupt flag is
cleared.
This programmable clock pulse generator provides the SCL clock pulses when the I
block is in the master transmitter or master receiver mode. It is switched off when the I
block is in slave mode. The I
Fig 51. Arbitration procedure
Fig 52. Serial clock synchronization
(1) Another device transmits serial data.
(2) Another device overrules a logic (dotted line) transmitted this I
(3) This I
(1) Another device pulls the SCL line low before this I
(2) Another device continues to pull the SCL line low after this I
(3) The SCL line is released , and the clock generator begins timing the HIGH time.
low. Arbitration is lost, and this I
transmitted. This I
the new master once it has won arbitration.
device effectively determines the (shorter) HIGH period.
released SCL. The I
effectively determines the (longer) LOW period.
SDA line
SCL line
shows the synchronization procedure.
SDA line
SCL line
2
C is in Slave Receiver mode but still generates clock pulses until the current byte has been
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
2
C will not generate clock pulses for the next byte. Data on SDA originates from
2
C clock generator is forced to wait until SCL goes HIGH. The other device
(1)
1
2
period
high
2
C output clock frequency and duty cycle is programmable
C block will stretch the SCL space duration after a byte has
(1)
(1)
2
2
Chapter 15: LPC111x/LPC11Cxx I2C-bus controller
C enters Slave Receiver mode.
period
low
(2)
3
(2)
(3)
4
2
C has timed a complete high time. The other
(1)
2
(3)
C has timed a complete low time and
2
C master by pulling the SDA line
8
UM10398
© NXP B.V. 2012. All rights reserved.
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C
2
C