LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 23

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
Table 7.
UM10398
User manual
Name
-
PDSLEEPCFG
PDAWAKECFG
PDRUNCFG
-
DEVICE_ID
Register overview: system control block (base address 0x4004 8000)
3.5.1 System memory remap register
3.5.2 Peripheral reset control register
Access
-
R/W
R/W
R/W
-
R
The system memory remap register selects whether the ARM interrupt vectors are read
from the boot ROM, the flash, or the SRAM. By default, the flash memory is mapped to
address 0x0000 0000. When the MAP bits in the SYSMEMREMAP register are set to 0x0
or 0x1, the boot ROM or RAM respectively are mapped to the bottom 512 bytes of the
memory map (addresses 0x0000 0000 to 0x0000 0200).
Table 8.
This register allows software to reset the SPI and I2C peripherals. Writing a zero to the
SSP0/1_RST_N or I2C_RST_N bits resets the SPI0/1 or I2C peripheral. Writing a one
de-asserts the reset.
Remark: Before accessing the SPI and I2C peripherals, write a one to this register to
ensure that the reset signals to the SPI and I2C are de-asserted.
Table 9.
Bit
1:0
31:2
Bit
0
Symbol
MAP
-
Symbol
SSP0_RST_N
Address offset Description
0x210 - 0x22C
0x230
0x234
0x238
0x23C - 0x3F0
0x3F4
System memory remap register (SYSMEMREMAP, address 0x4004 8000) bit
description
Peripheral reset control register (PRESETCTRL, address 0x4004 8004) bit
description
All information provided in this document is subject to legal disclaimers.
Value
0x0
0x1
0x2
-
Rev. 12 — 24 September 2012
Chapter 3: LPC111x/LPC11Cxx System configuration (SYSCON)
Value
0
1
Reserved
Power-down states after wake-up from
Deep-sleep mode
Power-down configuration register
Reserved
Device ID register 0 for parts LPC1100,
LPC1100C, LPC1100L.
Power-down states in Deep-sleep mode
System memory remap
Description
Boot Loader Mode. Interrupt vectors are re-mapped to Boot
ROM.
User RAM Mode. Interrupt vectors are re-mapped to Static
RAM.
User Flash Mode. Interrupt vectors are not re-mapped and
reside in Flash.
Reserved
Description
SPI0 reset control
Resets the SPI0 peripheral.
SPI0 reset de-asserted.
…continued
Reset
value
-
0x0000
0000
0x0000
EDF0
0x0000
EDF0
-
part
dependent
UM10398
© NXP B.V. 2012. All rights reserved.
Reference
-
Table 41
Table 42
Table 43
-
Table 44
23 of 538
Reset
value
10
0x00
Reset
value
0