LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 33

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
3.5.21 CLKOUT clock source select register
3.5.22 CLKOUT clock source update enable register
Table 27.
This register configures the clkout_clk signal to be output on the CLKOUT pin. All three
oscillators and the main clock can be selected for the clkout_clk clock.
The CLKOUTCLKUEN register (see
for the update to take effect.
Remark: When switching clock sources, both clocks must be running before the clock
source is updated.
Table 28.
This register updates the clock source of the CLKOUT pin with the new clock after the
CLKOUTCLKSEL register has been written to. In order for the update to take effect at the
input of the CLKOUT pin, first write a zero to the CLKCLKUEN register and then write a
one to CLKCLKUEN.
Remark: When switching clock sources, both clocks must be running before the clock
source is updated.
Table 29.
Bit
7:0
31:8
Bit
1:0
31:2
Bit
0
31:1
Symbol
DIV
-
Symbol
SEL
-
Symbol
ENA
-
WDT clock divider register (WDTCLKDIV, address 0x4004 80D8) bit description
CLKOUT clock source select register (CLKOUTCLKSEL, address 0x4004 80E0) bit
description
CLKOUT clock source update enable register (CLKOUTUEN, address 0x4004
80E4) bit description
All information provided in this document is subject to legal disclaimers.
WDT clock divider values
Description
0: Disable WDCLK.
1: Divide by 1.
to
255: Divide by 255.
Reserved
Value
0x0
0x1
0x2
0x3
-
Value
0
1
-
Rev. 12 — 24 September 2012
Chapter 3: LPC111x/LPC11Cxx System configuration (SYSCON)
CLKOUT clock source
IRC oscillator
System oscillator
Main clock
Description
Watchdog oscillator
Reserved
Description
Enable CLKOUT clock source update
No change
Update clock source
Reserved
Section
3.5.22) must be toggled from LOW to HIGH
UM10398
© NXP B.V. 2012. All rights reserved.
Reset value
0x00
0x00
Reset value
0x0
0x00
33 of 538
Reset
value
0x00
0x00