LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 362

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
Table 322: External Match Register (TMR32B0EMR - address 0x4001 403C and TMR32B1EMR - address0x4001 803C)
UM10398
User manual
3
5:4
7:6
Bit
0
1
2
9:8
Symbol Value Description
EM0
EM1
EM2
EM3
EMC0
EMC1
EMC2
bit description
0x0
0x1
0x2
0x3
0x0
0x1
0x2
0x3
0x0
0x1
0x2
0x3
External Match 0. This bit reflects the state of output CT32Bn_MAT0, whether or not this
output is connected to its pin. When a match occurs between the TC and MR0, this bit
can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality
of this output. This bit is driven to the CT32B0_MAT0/CT16B1_MAT0 pins if the match
function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
External Match 1. This bit reflects the state of output CT32Bn_MAT1, whether or not this
output is connected to its pin. When a match occurs between the TC and MR1, this bit
can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality
of this output. This bit is driven to the CT32B0_MAT1/CT16B1_MAT1 pins if the match
function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
External Match 2. This bit reflects the state of output CT32Bn_MAT2, whether or not this
output is connected to its pin. When a match occurs between the TC and MR2, this bit
can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality
of this output. This bit is driven to the CT32B0_MAT2/CT16B1_MAT2 pins if the match
function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
External Match 3. This bit reflects the state of output CT32Bn_MAT3, whether or not this
output is connected to its pin. When a match occurs between the TC and MR3, this bit
can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the
functionality of this output. This bit is driven to the CT32B0_MAT3/CT16B1_MAT3 pins if
the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
External Match Control 0. Determines the functionality of External Match 0.
Do Nothing.
Clear the corresponding External Match bit/output to 0 (CT32Bn_MATm pin is LOW if
pinned out).
Set the corresponding External Match bit/output to 1 (CT32Bn_MATm pin is HIGH if
pinned out).
Toggle the corresponding External Match bit/output.
External Match Control 1. Determines the functionality of External Match 1.
Do Nothing.
Clear the corresponding External Match bit/output to 0 (CT32Bn_MATm pin is LOW if
pinned out).
Set the corresponding External Match bit/output to 1 (CT32Bn_MATm pin is HIGH if
pinned out).
Toggle the corresponding External Match bit/output.
External Match Control 2. Determines the functionality of External Match 2.
Do Nothing.
Clear the corresponding External Match bit/output to 0 (CT32Bn_MATm pin is LOW if
pinned out).
Set the corresponding External Match bit/output to 1 (CT32Bn_MATm pin is HIGH if
pinned out).
Toggle the corresponding External Match bit/output.
Chapter 20: LPC1100/LPC1100C/LPC1100L series: 32-bit counter/timer
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
UM10398
© NXP B.V. 2012. All rights reserved.
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Reset
value
0
0
0
0
00
00
00