LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 521

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
Table 306. External Match Register (TMR16B0EMR -
Table 307. External match control . . . . . . . . . . . . . . . . . .348
Table 308. Count Control Register (TMR16B0CTCR -
Table 309. PWM Control Register (TMR16B0PWMC -
Table 310. Counter/timer pin description . . . . . . . . . . . . .355
Table 311. Register overview: 32-bit counter/timer 0 CT32B0
Table 312. Register overview: 32-bit counter/timer 1 CT32B1
Table 313: Interrupt Register (TMR32B0IR - address
Table 314: Timer Control Register (TMR32B0TCR - address
Table 315: Timer counter registers (TMR32B0TC, address
Table 316: Prescale registers (TMR32B0PR, address
Table 317: Prescale counter registers (TMR32B0PC,
Table 318: Match Control Register (TMR32B0MCR -
Table 319: Match registers (TMR32B0MR0 to 3, addresses
Table 320: Capture Control Register (TMR32B0CCR -
Table 321: Capture registers (TMR32B0CR0, addresses
Table 322: External Match Register (TMR32B0EMR -
Table 323. External match control . . . . . . . . . . . . . . . . . .363
Table 324: Count Control Register (TMR32B0CTCR -
Table 325: PWM Control Register (TMR32B0PWMC -
Table 326. Counter/timer pin description . . . . . . . . . . . . .369
Table 327. Register overview: 32-bit counter/timer 0 CT32B0
Table 328. Register overview: 32-bit counter/timer 1 CT32B1
UM10398
User manual
0x4000 C02C/30 and TMR16B1CR0/1, address
0x4001 002C/30) bit description . . . . . . . . . . .347
address 0x4000 C03C and TMR16B1EMR -
address 0x4001 003C) bit description . . . . . .347
address 0x4000 C070 and TMR16B1CTCR -
address 0x4001 0070) bit description. . . . . . .349
address 0x4000 C074 and TMR16B1PWMC-
address 0x4001 0074) bit description. . . . . . .350
(base address 0x4001 4000) . . . . . . . . . . . .355
(base address 0x4001 8000) . . . . . . . . . . . .356
0x4001 4000 and TMR32B1IR - address
0x4001 8000) bit description . . . . . . . . . . . . .357
0x4001 4004 and TMR32B1TCR - address
0x4001 8004) bit description . . . . . . . . . . . . .358
0x4001 4008 and TMR32B1TC 0x4001 8008) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .358
0x4001 400C and TMR32B1PR 0x4001 800C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .358
address 0x4001 4010 and TMR32B1PC
0x4001 8010) bit description . . . . . . . . . . . . .359
address 0x4001 4014 and TMR32B1MCR -
address 0x4001 8014) bit description. . . . . . .359
0x4001 4018 to 24 and TMR32B1MR0 to 3,
addresses 0x4001 8018 to 24) bit description 360
address 0x4001 4028 and TMR32B1CCR -
address 0x4001 8028) bit description. . . . . . .360
0x4001 402C and TMR32B1CR0, addresses
0x4001 802C) bit description . . . . . . . . . . . . .361
address 0x4001 403C and TMR32B1EMR -
address0x4001 803C) bit description . . . . . . .362
address 0x4001 4070 and TMR32B1TCR -
address 0x4001 8070) bit description . . . . . .364
0x4001 4074 and TMR32B1PWMC - 0x4001
8074) bit description . . . . . . . . . . . . . . . . . . . .364
(base address 0x4001 4000) . . . . . . . . . . . .370
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
Table 329: Interrupt Register (TMR32B0IR - address
Table 330: Timer Control Register (TMR32B0TCR - address
Table 331: Timer counter registers (TMR32B0TC, address
Table 332: Prescale registers (TMR32B0PR, address
Table 333: Prescale counter registers (TMR32B0PC,
Table 334: Match Control Register (TMR32B0MCR -
Table 335: Match registers (TMR32B0MR0 to 3, addresses
Table 336: Capture Control Register (TMR32B0CCR -
Table 337: Capture registers (TMR32B0CR0/1, addresses
Table 338: External Match Register (TMR32B0EMR -
Table 339. External match control . . . . . . . . . . . . . . . . . 377
Table 340: Count Control Register (TMR32B0CTCR -
Table 341: PWM Control Register (TMR32B0PWMC -
Table 342. Register overview: Watchdog timer (base
Table 343: Watchdog Mode register (WDMOD -
Table 344. Watchdog operating modes selection . . . . . . 387
Table 345: Watchdog Timer Constant register (WDTC -
Table 346: Watchdog Feed register (WDFEED -
Table 347: Watchdog Timer Value register (WDTV -
Table 348: Watchdog Timer Warning Interrupt register
Table 349: Watchdog Timer Window register (WDWINDOW
Table 350. Register overview: Watchdog timer (base
Table 351. Watchdog Mode register (WDMOD - address
Table 352. Watchdog operating modes selection . . . . . . 394
(base address 0x4001 8000) . . . . . . . . . . . . 371
0x4001 4000 and TMR32B1IR - address
0x4001 8000) bit description . . . . . . . . . . . . . 372
0x4001 4004 and TMR32B1TCR - address
0x4001 8004) bit description . . . . . . . . . . . . . 372
0x4001 4008 and TMR32B1TC 0x4001 8008) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 372
0x4001 400C and TMR32B1PR 0x4001 800C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
address 0x4001 4010 and TMR32B1PC
0x4001 8010) bit description . . . . . . . . . . . . . 373
address 0x4001 4014 and TMR32B1MCR -
address 0x4001 8014) bit description . . . . . . 373
0x4001 4018 to 24 and TMR32B1MR0 to 3,
addresses 0x4001 8018 to 24) bit description 375
address 0x4001 4028 and TMR32B1CCR -
address 0x4001 8028) bit description . . . . . . 375
0x4001 402C/30 and TMR32B1CR0/1, addresses
0x4001 802C/30) bit description . . . . . . . . . . 376
address 0x4001 403C and TMR32B1EMR -
address0x4001 803C) bit description . . . . . . 376
address 0x4001 4070 and TMR32B1TCR -
address 0x4001 8070) bit description . . . . . 378
0x4001 4074 and TMR32B1PWMC - 0x4001
8074) bit description. . . . . . . . . . . . . . . . . . . . 379
address 0x4000 4000) . . . . . . . . . . . . . . . . . . 386
0x4000 4000) bit description . . . . . . . . . . . . . 386
0x4000 4004) bit description . . . . . . . . . . . . . 388
0x4000 4008) bit description . . . . . . . . . . . . . 388
0x4000 400C) bit description . . . . . . . . . . . . . 388
(WDWARNINT - 0x4000 4014) bit description389
- 0x4000 4018) bit description . . . . . . . . . . . . 389
address 0x4000 4000) . . . . . . . . . . . . . . . . . . 393
0x4000 4000) bit description . . . . . . . . . . . . . 393
Chapter 29: Supplementary information
UM10398
© NXP B.V. 2012. All rights reserved.
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