LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 522

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
Table 353. Watchdog Constant register (WDTC - address
Table 354. Watchdog Feed register (WDFEED - address
Table 355. Watchdog Timer Value register (WDTV - address
Table 356. Register overview: SysTick timer (base address
Table 357. SysTick Timer Control and status register
Table 358. System Timer Reload value register (SYST_RVR
Table 359. System Timer Current value register (SYST_CVR
Table 360. System Timer Calibration value register
Table 361. ADC pin description . . . . . . . . . . . . . . . . . . . .401
Table 362. Register overview: ADC (base address 0x4001
Table 363. A/D Control Register (AD0CR - address
Table 364. A/D Global Data Register (AD0GDR - address
Table 365. A/D Interrupt Enable Register (AD0INTEN -
Table 366. A/D Data Registers (AD0DR0 to AD0DR7 -
Table 367. A/D Status Register (AD0STAT - address
Table 368. LPC111x/LPC11Cx flash configurations. . . . .406
Table 369. LPC111x flash configuration (LPC1100,
Table 370. LPC1100XL flash configuration . . . . . . . . . . . 411
Table 371. Code Read Protection options . . . . . . . . . . . .413
Table 372. Code Read Protection hardware/software
Table 373. ISP commands allowed for different CRP
Table 374. UART ISP command summary . . . . . . . . . . .416
Table 375. UART ISP Unlock command . . . . . . . . . . . . .417
Table 376. UART ISP Set Baud Rate command . . . . . . .417
Table 377. UART ISP Echo command . . . . . . . . . . . . . .417
Table 378. UART ISP Write to RAM command . . . . . . . .418
Table 379. UART ISP Read Memory command . . . . . . .418
Table 380. UART ISP Prepare sector(s) for write operation
Table 381. UART ISP Copy RAM to flash command. . . .420
Table 382. UART ISP Go command . . . . . . . . . . . . . . . .420
Table 383. UART ISP Erase sector command . . . . . . . .421
UM10398
User manual
0x4000 4004) bit description . . . . . . . . . . . . .394
0x4000 4008) bit description . . . . . . . . . . . . .395
0x4000 000C) bit description . . . . . . . . . . . . .395
0xE000 E000) . . . . . . . . . . . . . . . . . . . . . . . . .397
(SYST_CSR - 0xE000 E010) bit description .398
- 0xE000 E014) bit description . . . . . . . . . . . .398
- 0xE000 E018) bit description . . . . . . . . . . . .398
(SYST_CALIB - 0xE000 E01C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .399
C000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .401
0x4001 C000) bit description . . . . . . . . . . . . .402
0x4001 C004) bit description . . . . . . . . . . . . .403
address 0x4001 C00C) bit description . . . . . .404
addresses 0x4001 C010 to 0x4001 C02C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .404
0x4001 C030) bit description . . . . . . . . . . . . .405
LPC1100L, LPC1100C series) . . . . . . . . . . . . 411
interaction . . . . . . . . . . . . . . . . . . . . . . . . . . . .413
levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .414
command . . . . . . . . . . . . . . . . . . . . . . . . . . . .419
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
Table 384. UART ISP Blank check sector command . . . 421
Table 385. UART ISP Read Part Identification command421
Table 386. LPC111x and LPC11Cxx part identification
Table 387. UART ISP Read Boot Code version number
Table 388. UART ISP Compare command . . . . . . . . . . . 423
Table 389. UART ISP ReadUID command . . . . . . . . . . . 424
Table 390. UART ISP Return Codes Summary . . . . . . . 424
Table 391. C_CAN ISP and UART ISP command
Table 392. C_CAN ISP object directory . . . . . . . . . . . . . 426
Table 393. C_CAN ISP SDO abort codes. . . . . . . . . . . . 428
Table 394. IAP Command Summary . . . . . . . . . . . . . . . 430
Table 395. IAP Prepare sector(s) for write operation
Table 396. IAP Copy RAM to flash command. . . . . . . . . 432
Table 397. IAP Erase Sector(s) command . . . . . . . . . . . 432
Table 398. IAP Blank check sector(s) command . . . . . . 433
Table 399. IAP Read Part Identification command . . . . . 433
Table 400. IAP Read Boot Code version number
Table 401. IAP Compare command . . . . . . . . . . . . . . . . 434
Table 402. IAP Reinvoke ISP . . . . . . . . . . . . . . . . . . . . . 435
Table 403. IAP ReadUID command . . . . . . . . . . . . . . . . 435
Table 404. IAP Erase page command . . . . . . . . . . . . . . 435
Table 405. IAP Status Codes Summary . . . . . . . . . . . . . 436
Table 406. Memory mapping in debug mode . . . . . . . . . 436
Table 407. Flash configuration register (FLASHCFG,
Table 408. Register overview: FMC (base address 0x4003
Table 409. Flash Module Signature Start register
Table 410. Flash Module Signature Stop register (FMSSTOP
Table 411. FMSW0 register bit description (FMSW0,
Table 412. FMSW1 register bit description (FMSW1,
Table 413. FMSW2 register bit description (FMSW2,
Table 414. FMSW3 register bit description (FMSW3,
Table 415. Flash module Status register (FMSTAT - 0x4003
Table 416. Flash Module Status Clear register (FMSTATCLR
Table 417. Serial Wire Debug pin description. . . . . . . . . 442
Table 418. Summary of processor mode and stack use
numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422
command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423
summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431
command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433
address 0x4003 C010) bit description . . . . . . 437
C000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438
(FMSSTART - 0x4003 C020) bit description . 439
- 0x4003 C024) bit description . . . . . . . . . . . . 439
address: 0x4003 C02C) . . . . . . . . . . . . . . . . 439
address: 0x4003 C030) . . . . . . . . . . . . . . . . . 439
address: 0x4003 C034) . . . . . . . . . . . . . . . . . 439
address: 0x4003 40C8) . . . . . . . . . . . . . . . . 439
CFE0) bit description . . . . . . . . . . . . . . . . . . . 440
- 0x0x4003 CFE8) bit description. . . . . . . . . . 440
options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446
Chapter 29: Supplementary information
UM10398
© NXP B.V. 2012. All rights reserved.
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