LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 464

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
28.5 Instruction set
UM10398
User manual
28.4.5.1.3 Sleep-on-exit
28.4.5.2.1 Wake-up from WFI or sleep-on-exit
28.4.5.2.2 Wake-up from WFE
28.4.5.2 Wake-up from sleep mode
28.4.5.3 Power management programming hints
28.5.1 Instruction set summary
If the SLEEPONEXIT bit of the SCR is set to 1, when the processor completes the
execution of an exception handler and returns to Thread mode it immediately enters sleep
mode. Use this mechanism in applications that only require the processor to run when an
interrupt occurs.
The conditions for the processor to wake-up depend on the mechanism that caused it to
enter sleep mode.
Normally, the processor wakes up only when it detects an exception with sufficient priority
to cause exception entry.
Some embedded systems might have to execute system restore tasks after the processor
wakes up, and before it executes an interrupt handler. To achieve this set the PRIMASK
bit to 1. If an interrupt arrives that is enabled and has a higher priority than current
exception priority, the processor wakes up but does not execute the interrupt handler until
the processor sets PRIMASK to zero. For more information about PRIMASK, see
Section
The processor wakes up if:
In addition, if the SEVONPEND bit in the SCR is set to 1, any new pending interrupt
triggers an event and wakes up the processor, even if the interrupt is disabled or has
insufficient priority to cause exception entry. For more information about the SCR see
Section
ISO/IEC C cannot directly generate the WFI, WFE, and SEV instructions. The CMSIS
provides the following intrinsic functions for these instructions:
void __WFE(void) // Wait for Event
void __WFI(void) // Wait for Interrupt
void __SEV(void) // Send Event
The processor implements a version of the Thumb instruction set.
supported instructions.
Remark: In
•
•
it detects an exception with sufficient priority to cause exception entry
in a multiprocessor system, another processor in the system executes a SEV
instruction.
28–28.4.1.3.6.
28–28.6.3.5.
Table 429
Chapter 28: LPC111x/LPC11Cxx Appendix: ARM Cortex-M0 reference
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
Table 429
UM10398
© NXP B.V. 2012. All rights reserved.
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