LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 510

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
28.7 Cortex-M0 instruction summary
UM10398
User manual
Table 462. Cortex M0- instruction summary
Operation
Move
Add
Add
Subtract
Multiply
Compare
Logical
Shift
Rotate
Chapter 28: LPC111x/LPC11Cxx Appendix: ARM Cortex-M0 reference
All information provided in this document is subject to legal disclaimers.
Description
8-bit immediate
Lo to Lo
Any to Any
Any to PC
3-bit immediate
All registers Lo
Any to Any
Any to PC
8-bit immediate
With carry
Immediate to SP
Form address from SP
Form address from PC
Lo and Lo
3-bit immediate
8-bit immediate
With carry
Immediate from SP
Negate
Multiply
Compare
Negative
Immediate
AND
Exclusive OR
OR
Bit clear
Move NOT
AND test
Logical shift left by immediate
Logical shift left by register
Logical shift right by immediate
Logical shift right by register
Arithmetic shift right
Arithmetic shift right by register
Rotate right by register
Rev. 12 — 24 September 2012
Assembler
MOVS Rd, #<imm>
MOVS Rd, Rm
MOV Rd, Rm
MOV PC, Rm
ADDS Rd, Rn, #<imm>
ADDS Rd, Rn, Rm
ADD Rd, Rd, Rm
ADD PC, PC, Rm
ADDS Rd, Rd, #<imm>
ADCS Rd, Rd, Rm
ADD SP, SP, #<imm>
ADD Rd, SP, #<imm>
ADR Rd, <label>
SUBS Rd, Rn, Rm
SUBS Rd, Rn, #<imm>
SUBS Rd, Rd, #<imm>
SBCS Rd, Rd, Rm
SUB SP, SP, #<imm>
RSBS Rd, Rn, #0
MULS Rd, Rm, Rd
CMP Rn, Rm
CMN Rn, Rm
CMP Rn, #<imm>
ANDS Rd, Rd, Rm
EORS Rd, Rd, Rm
ORRS Rd, Rd, Rm
BICS Rd, Rd, Rm
MVNS Rd, Rm
TST Rn, Rm
LSLS Rd, Rm, #<shift>
LSLS Rd, Rd, Rs
LSRS Rd, Rm, #<shift>
LSRS Rd, Rd, Rs
ASRS Rd, Rm, #<shift>
ASRS Rd, Rd, Rs
RORS Rd, Rd, Rs
UM10398
© NXP B.V. 2012. All rights reserved.
Cycles
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