LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 364

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
20.7.12 PWM Control Register (TMR32B0PWMC and TMR32B1PWMC)
Table 324: Count Control Register (TMR32B0CTCR - address 0x4001 4070 and TMR32B1TCR
The PWM Control Register is used to configure the match outputs as PWM outputs. Each
match output can be independently set to perform either as PWM output or as match
output whose function is controlled by the External Match Register (EMR).
For each timer, a maximum of three-single edge controlled PWM outputs can be selected
on the MATn[2:0] outputs. One additional match register determines the PWM cycle
length. When a match occurs in any of the other match registers, the PWM output is set to
HIGH. The timer is reset by the match register that is configured to set the PWM cycle
length. When the timer is reset to zero, all currently HIGH match outputs configured as
PWM outputs are cleared.
Table 325: PWM Control Register (TMR32B0PWMC - 0x4001 4074 and TMR32B1PWMC -
Bit
1:0
3:2
31:4
Bit
0
Symbol
CTM
CIS
-
Symbol
PWMEN0
- address 0x4001 8070) bit description
0x4001 8074) bit description
Chapter 20: LPC1100/LPC1100C/LPC1100L series: 32-bit counter/timer
All information provided in this document is subject to legal disclaimers.
Value
0x0
0x1
0x2
0x3
0x0
0x1
0x2
0x3
-
Value
0
1
Rev. 12 — 24 September 2012
Description
Counter/Timer Mode. This field selects which rising PCLK
edges can increment Timer’s Prescale Counter (PC), or
clear PC and increment Timer Counter (TC).
Timer Mode: every rising PCLK edge
Timer Mode: every rising PCLK edge
Counter Mode: TC is incremented on rising edges on the
CAP input selected by bits 3:2.
Counter Mode: TC is incremented on falling edges on the
CAP input selected by bits 3:2.
Counter Mode: TC is incremented on both edges on the CAP
input selected by bits 3:2.
Count Input Select. When bits 1:0 in this register are not 00,
these bits select which CAP pin is sampled for clocking:
CT32Bn_CAP0
Reserved
Reserved
Reserved
Note: If Counter mode is selected in the TnCTCR, the 3 bits
for that input in the Capture Control Register (TnCCR) must
be programmed as 000.
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Description
PWM channel 0 enable
CT32Bn_MAT0 is controlled by EM0.
PWM mode is enabled for CT32Bn_MAT0.
UM10398
© NXP B.V. 2012. All rights reserved.
Reset
value
0
364 of 538
Reset
value
00
00
NA