LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 365

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
20.7.13 Rules for single edge controlled PWM outputs
Table 325: PWM Control Register (TMR32B0PWMC - 0x4001 4074 and TMR32B1PWMC -
Note: When the match outputs are selected to function as PWM outputs, the timer reset
(MRnR) and timer stop (MRnS) bits in the Match Control Register MCR must be set to 0
except for the match register setting the PWM cycle length. For this register, set the
MRnR bit to 1 to enable the timer reset when the timer value matches the value of the
corresponding match register.
Bit
1
2
3
31:4
1. All single edge controlled PWM outputs go LOW at the beginning of each PWM cycle
2. Each PWM output will go HIGH when its match value is reached. If no match occurs
3. If a match value larger than the PWM cycle length is written to the match register, and
4. If a match register contains the same value as the timer reset value (the PWM cycle
5. If a match register is set to zero, then the PWM output will go to HIGH the first time the
(timer is set to zero) unless their match value is equal to zero.
(i.e. the match value is greater than the PWM cycle length), the PWM output remains
continuously LOW.
the PWM signal is HIGH already, then the PWM signal will be cleared with the start of
the next PWM cycle.
length), then the PWM output will be reset to LOW on the next clock tick after the
timer reaches the match value. Therefore, the PWM output will always consist of a
one clock tick wide positive pulse with a period determined by the PWM cycle length
(i.e. the timer reload value).
timer goes back to zero and will stay HIGH continuously.
Symbol
PWMEN1
PWMEN2
PWMEN3
-
0x4001 8074) bit description
Chapter 20: LPC1100/LPC1100C/LPC1100L series: 32-bit counter/timer
All information provided in this document is subject to legal disclaimers.
Value
0
1
0
1
0
1
Rev. 12 — 24 September 2012
Description
PWM channel 1 enable
CT32Bn_MAT1 is controlled by EM1.
PWM mode is enabled for CT32Bn_MAT1.
PWM channel 2 enable
CT32Bn_MAT2 is controlled by EM2.
PWM mode is enabled for CT32Bn_MAT2.
PWM channel 3 enable
Note: It is recommended to use match channel 3 to set
the PWM cycle.
CT32Bn_MAT3 is controlled by EM3.
PWM mode is enabled for CT32Bn_MAT3.
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
UM10398
© NXP B.V. 2012. All rights reserved.
Reset
value
0
0
0
NA
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