LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 202

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
Fig 32. Auto-CTS Functional Timing
UART1 TX
CTS1 pin
13.5.9 UART Line Status Register (U0LSR - 0x4000 8014, Read Only)
start
bits0..7
While starting transmission of the initial character, the CTS signal is asserted.
Transmission will stall as soon as the pending transmission has completed. The UART will
continue transmitting a 1 bit as long as CTS is de-asserted (high). As soon as CTS gets
de-asserted, transmission resumes and a start bit is sent followed by the data bits of the
next character.
The U0LSR is a Read Only register that provides status information on the UART TX and
RX blocks.
Table 195. UART Line Status Register (U0LSR - address 0x4000 8014, Read Only) bit
Bit Symbol
0
1
2
RDR
OE
PE
stop
description
All information provided in this document is subject to legal disclaimers.
Value
0
1
0
1
0
1
Rev. 12 — 24 September 2012
Description
Receiver Data Ready. U0LSR[0] is set when the U0RBR holds
an unread character and is cleared when the UART RBR FIFO
is empty.
U0RBR is empty.
U0RBR contains valid data.
Overrun Error. The overrun error condition is set as soon as it
occurs. A U0LSR read clears U0LSR[1]. U0LSR[1] is set when
UART RSR has a new character assembled and the UART
RBR FIFO is full. In this case, the UART RBR FIFO will not be
overwritten and the character in the UART RSR will be lost.
Overrun error status is inactive.
Overrun error status is active.
Parity Error. When the parity bit of a received character is in
the wrong state, a parity error occurs. A U0LSR read clears
U0LSR[2]. Time of parity error detection is dependent on
U0FCR[0].
Note: A parity error is associated with the character at the top
of the UART RBR FIFO.
Parity error status is inactive.
Parity error status is active.
start
bits0..7
stop
Chapter 13: LPC111x/LPC11Cxx UART
start
UM10398
© NXP B.V. 2012. All rights reserved.
bits0..7
202 of 538
stop
Reset
Value
0
0
0