LPC1112FHN33/203,5 NXP Semiconductors, LPC1112FHN33/203,5 Datasheet - Page 266

• Manufacturer Part Number: LPC1112FHN33/203,5
• Description: ARM Microcontrollers - MCU Cortex-M0 16kB flash up to 4 kB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN33/203,5

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Operating Temperature Range: - 65 C to + 150 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
UM10398
User manual
15.10.6.4 I
15.10.6.5 Bus error
15.10.7 I
An I
the bus. If the SCL line is obstructed (pulled LOW) by a device on the bus, no further serial
transfer is possible, and the problem must be resolved by the device that is pulling the
SCL bus line LOW.
Typically, the SDA line may be obstructed by another device on the bus that has become
out of synchronization with the current bus master by either missing a clock, or by sensing
a noise pulse as a clock. In this case, the problem can be solved by transmitting additional
clock pulses on the SCL line (see
dedicated time-out timer to detect an obstructed bus, but this can be implemented using
another timer in the system. When detected, software can force clocks (up to 9 may be
required) on SCL until SDA is released by the offending device. At that point, the slave
may still be out of synchronization, so a START should be generated to insure that all I
peripherals are synchronized.
A bus error occurs when a START or STOP condition is detected at an illegal position in
the format frame. Examples of illegal positions are during the serial transfer of an address
byte, a data bit, or an acknowledge bit.
The I
a master or an addressed slave. When a bus error is detected, the I
switches to the not addressed slave mode, releases the SDA and SCL lines, sets the
interrupt flag, and loads the status register with 0x00. This status code may be used to
vector to a state service routine which either attempts the aborted serial transfer again or
simply recovers from the error condition as shown in
This section provides examples of operations that must be performed by various I
service routines. This includes:
2
2
Fig 59. Recovering from a bus obstruction caused by a LOW level on SDA
•
•
•
C-bus obstructed by a LOW level on SCL or SDA
C state service routines
2
Initialization of the I
I
The 26 state service routines providing support for all four I
2
C-bus hang-up can occur if either the SDA or SCL line is held LOW by any device on
2
(1) Unsuccessful attempt to send a START condition.
(2) SDA line is released.
(3) Successful attempt to send a START condition. State 08H is entered.
C Interrupt Service
C hardware only reacts to a bus error when it is involved in a serial transfer either as
STA flag
SDA line
SCL line
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
2
C block after a Reset.
(1)
Figure
Chapter 15: LPC111x/LPC11Cxx I2C-bus controller
(1)
59). The I
2
(2)
C interface does not include a
Table
condition
241.
(3)
start
2
C operating modes.
2
C block immediately
UM10398
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2
C state
2
C