ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 108

• Manufacturer Part Number: ALXD800EEXJ2VD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

5.5.2
5.5.2.1
MSR Address
Type
Reset Value
5.5.2.2
MSR Address
Type
Reset Value
108
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:40
63:0
39:0
Bit
Bit
CPU Core Specific MSRs
Time Stamp Counter MSR (TSC_MSR)
Performance Event Counter 0 MSR (PERF_CNT0_MSR)
Name
TSC
Name
RSVD
PERF_CNT0
00000010h
R/W
00000000_00000000h
000000C1h
R/W
00000000_00000000h
33234C
Description
Time Stamp Counter. This register is the 64-bit Intel-compatible time stamp counter,
also readable via the RDTSC instruction.
Bus Controller Configuration 0 Register (MSR 00001900h) contains configuration bits
that determine if TSC counts during SMM, DMM, or Suspend modes.
Writes to this register clears the upper DWORD to 0 to be compatible with Intel’s imple-
mentation. The lower DWORD is written normally.
Description
Reserved. Write as read.
Performance Event Counter 0. This register is a 40-bit event counter used to count
events or conditions inside of the CPU Core. This counter is controlled by Performance
Event Counter 0 Select MSR (MSR 00000186h).
PERF_CNT0_MSR Bit Descriptions
PERF_CNT0_MSR Register Map
RSVD
TSC_MSR Bit Descriptions
TSC_MSR Register Map
PERF_CNT0 (Low DWORD)
TSC (High DWORD)
TSC (Low DWORD)
AMD Geode™ LX Processors Data Book
9
9
8
8
CPU Core Register Descriptions
7
7
PERF_CNT0 (High Byte)
6
6
5
5
4
4
3
3
2
2
1
1
0
0