ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 530

• Manufacturer Part Number: ALXD800EEXJ2VD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

530
23:18
17:16
15:13
11:10
Instruction
Bit
9:7
2:0
1FFFEB0h
1FFFFDFh
1FFFFFDh
1FFFFFEh
1FFFFFFh
123FFFAh
127FFFAh
24
12
6
5
4
3
Name
TAPSCAN#
USER[5:0]
bistEnable[4:3]
clkRatio[2:0]#
freezeMode
setupMode[1:0]#
bistEnable[2:0]
testMode#
forceDis#
selectJtagOut#
selectJtagIn#
OP[2:0]
Length
33234C
441
DR
29
32
8
8
1
1
Table 6-81. TAP Control Instructions (25-Bit IR)
IR Name
MULTISCAN
TRISTATE
BISTDR
IDCODE
BYPASS_MODES
REVID
BYPASS
User bits used to identify an internal scan chain or, if bit 24 is high, to access a special
Bits 4 and 3 of the BIST enable for individual BIST chain access.
Not used in the Geode™ LX processor (bits should always be high); clock ratio controls
Active low bit that allows boundary scan cells to control pads.
Active low bit that allows boundary scan cells to drive data into core logic of chip.
Opcode that selects how the JTAG chains are wired together.
Description
Also USER[6] in the design. This is a user bit added by AMD; low indicates that an inter-
nal scan chain is accessed by the TAP.
internal DR, as shown in Table 6-81.
for LogicBist.
Not used in the Geode LX processor (should always be high); another clock control sig-
nal.
Not used in the Geode LX processor (should always be high); these are special BIST
controller bits.
BIST[2:0] of BIST enable. Works in conjunction with bits [17:16].
Active low TEST_MODE for entire chip. Puts internal logic into scan test mode.
Active low bit TRI-STATEs all output pins.
Table 6-82. TAP Instruction Bits
Parallel RAM BIST - internal data register (for chip test)
ID Code = 0D5A1003h
Description
This register is read/write.
Should be 10h for initial Geode™ LX processor (upper nibble
is major rev, lower nibble is minor) changes for each metal spin
Parallel scan (muxes scan outputs onto many chip pins)
Put chip into TRI-STATE and comparison mode
Bypass; IEEE 1149.1 spec requires all 1s to be bypass
AMD Geode™ LX Processors Data Book
GeodeLink™ Control Processor