ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 69

• Manufacturer Part Number: ALXD800EEXJ2VD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

GLIU Register Descriptions
4.2.2.12 Arbitration2 (ARB2)
MSR Address
Type
Reset Value
AMD Geode™ LX Processors Data Book
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:8
63:4
Bit
Bit
2:0
7
6
5
4
3
2
1
0
3
Name
RSVD
SLAVE_DIS7
SLAVE_DIS6
SLAVE_DIS5
SLAVE_DIS4
SLAVE_DIS3
SLAVE_DIS2
SLAVE_DIS1
SLAVE_DIS0
Name
RSVD
THROT_EN
THRESH
GLIU0: 1000008Dh
GLIU1: 4000008Dh
R/W
00000000_00000000h
Description
Reserved.
Arbitration Throttling Enable. When set, arbitration is prevented in this GLIU if the
other GLIU is retreating a priority above the THRESH priority.
Priority Threshold. See THROT_EN description. Priority threshold value must be 4 or
less.
0: Disable.
1: Enable.
Description
Reserved.
Slave Transactions Disable for Port 7 (GLIU0: Not Used; GLIU1: Not Used). Write
1 to disable slave transactions to Port 7.
Slave Transactions Disable for Port 6 (GLIU0: Not Used; GLIU1: SB (Security
Block)). Write 1 to disable slave transactions to Port 6.
Slave Transactions Disable for Port 5 (GLIU0: GP; GLIU1: VIP). Write 1 to disable
slave transactions to Port 5.
Slave Transactions Disable for Port 4 (GLIU0: DC; GLIU1: GLPCI). Write 1 to dis-
able slave transactions to Port 4.
Slave Transactions Disable for Port 3 (GLIU0: CPU Core; GLIU1: GLCP). Write 1 to
disable slave transactions to Port 3.
Slave Transactions Disable for Port 2 (GLIU0: Interface to GLIU1; GLIU1: VP).
Write 1 to disable slave transactions to Port 2.
Slave Transactions Disable for Port 1 (GLIU0: GLMC; GLIU1: Interface to GLIU0).
Write 1 to disable slave transactions to Port 1.
Slave Transactions Disable for Port 0 (GLIU0: GLIU; GLIU1: GLIU). Write 1 to dis-
able slave transactions to Port 0.
GLIU_SLV Bit Descriptions
ARB2 Bit Descriptions
ARB2 Register Map
RSVD
RSVD
9
8
33234C
7
6
5
4
3
2
THRESH
1
0
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