ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 82

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ALXD800EEXJ2VD

Manufacturer Part Number
ALXD800EEXJ2VD
Description
Manufacturer
AMD (ADVANCED MICRO DEVICES)
Datasheet

Specifications of ALXD800EEXJ2VD

Operating Temperature (min)
0C
Operating Temperature (max)
85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant

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4.2.4.4
GLIU0
MSR Address
Type
Reset Value
See Table 4.1.3.1 "Memory Routing and Translation" on page 47 for details on the descriptor usage.
82
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:61
59:40
39:20
PDID1
19:0
Bit
60
P2D Range Offset Descriptor (P2D_RO)
Name
PDID1
PCMP_BIZ
POFFSET
PMAX
PMIN
P2D_RO[3:0]
10000029h-1000002Bh
R/W
00000000_000FFFFFh
PMAX
33234C
Description
Descriptor Destination ID. These bits define which Port to route the request to, if it is a
‘hit’ based on the other settings in this register.
000: Port 0 = GLIU0: GLIU; GLIU1: GLIU
001: Port 1 = GLIU0: GLMC; GLIU1: Interface to GLIU0
010: Port 2 = GLIU0: Interface to GLIU1; GLIU1: VP
011: Port 3 = GLIU0: CPU Core; GLIU1: GLCP
100: Port 4 = GLIU0: DC; GLIU1: GLPCI
101: Port 5 = GLIU0: GP; GLIU1: VIP
110: Port 6 = GLIU0: Not Used; GLIU1: SB (Security Block)
111: Port 7 = GLIU0: Not Used; GLIU1: Not Used
Compare Bizzaro Flag.
0: Consider only transactions whose Bizzaro flag is low as a potentially valid address hit.
1: Consider only transactions whose Bizarro flag is high as a potentially valid address hit.
Physical Memory Address 2’s Comp Offset. 2s complement offset that is added to
physical address on a hit.
Physical Memory Address Max. These bits form the value denoting the upper (ending)
address of the physical memory, which is compared to determine a hit.
Physical Memory Address Min. These bits form the value denoting the lower (starting)
address of the physical memory, which is compared to determine a hit. Hence, a hit
occurs if the physical address [31:12] >= PMIN and <= PMAX.
A low Bizarro flag indicates a normal transaction cycle such as a memory or I/O.
A high Bizzaro flag indicates a ‘special’ transaction, such as a PCI Shutdown or Halt
cycle.
P2D_RO Bit Descriptions
P2D_RO Register Map
OFFSET
PMIN
AMD Geode™ LX Processors Data Book
9
8
7
GLIU Register Descriptions
6
5
PMAX
4
3
2
1
0

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