ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 92

• Manufacturer Part Number: ALXD800EEXJ2VD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

5.4
The System Register Set, shown in Table 5-5, consists of
registers not generally used by application programmers.
These registers are either initialized by the system BIOS or
employed by system level programmers who generate
operating systems and memory management programs.
Associated with the System Register Set are certain tables
and registers that are listed in Table 5-5.
The Control registers control certain aspects of the CPU
Core such as paging, coprocessor functions, and segment
protection.
The CPU Core Configuration registers are used to initial-
ize, provide for, test or define most of the features of the
CPU Core. The attributes of these registers include:
• CPU setup - Enable cache, features, operating modes.
• Debug support - Provide debugging facilities for the
• Built-in Self-test (BIST) support.
• Test - Support a mechanism to test the contents of the
• In-Circuit Emulation (ICE) - Provide for a alternative
• CPU identification - Allow the BIOS and other software
• Power Management.
• Performance Monitoring - Enables test software to
The Descriptor Table registers point to tables used to
manage memory segments and interrupts.
The Task State register points to the Task State Segment,
which is used to save and load the processor state when
switching tasks.
Table 5-5 lists the System Register Sets along with their
size and function.
92
Geode™ LX processor and enable the use of data
access breakpoints and code execution breakpoints.
on-chip caches and the Translation Lookaside Buffers
(TLBs).
accessing path to support an ICE.
to identify the specific CPU and stepping.
measure the performance of application software.
System Register Set
33234C
Group
Control
Registers
CPU Core
Configuration
Registers
Descriptor
Table
Registers
Task Register
Performance
Registers
Table 5-5. System Register Set
Name
CR0
CR2
CR3
CR4
PLn
IMn
DMn
BCn
FPUn
GDTR
IDTR
LDTR
TR
PCRn
AMD Geode™ LX Processors Data Book
Function
System Control
Register
Page Fault Linear
Address Register
Page Directory Base
Register
Feature Enables
Pipeline
Control Registers
Instruction Memory
Control Registers
Data Memory Con-
trol Registers
Bus Controller Con-
trol Registers
Floating Point Unit
Shadow Registers
GDT Register
IDT Register
LDT Register
Task Register
Performance
Control Registers
CPU Core
Width
(Bits)
32
32
16
16
32
32
32
64
64
64
64
64
32
8