ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 192

• Manufacturer Part Number: ALXD800EEXJ2VD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

5.5.2.105 Bus Controller Extended Debug Registers 3 and 2 MSR (BXDR3_BXDR2_MSR)
MSR Address
Type
Reset Value
5.5.2.106 Bus Controller Extended Debug Registers 6 and 7 MSR (BXDR6_BXDR7_MSR)
MSR Address
Type
Reset Value
BXDR6 (bits [31:0]) contains the status of the extended bus controller breakpoints. When a breakpoint occurs, the corre-
sponding status bit is set in this register. The status bits remain set until cleared by an MSR write.
BXDR7 (bits [63:32]) is used to enable and specify the type of BXDR0-BXDR3. BXDR7 is also used to specify the length of
the breakpoint. For example, if BXDR0 is set to 00000006h, and BXDR7 indicates it has a length of 2 bytes, then an access
to 00000006h or 00000007h triggers the breakpoint. BXDR0 and BXDR1 can be paired to specify a range breakpoint if the
LEN0 or LEN1 field of BXDR7 is set accordingly. BXDR2 and BXDR3 can be paired to specify a range breakpoint if the
LEN2 or LEN3 field of BXDR7 is set accordingly.
192
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:32
63:32
31:0
31:0
Bit
Bit
TYPE3
Name
BXDR1_PHYS_
ADDR
BXDR0_PHYS_
ADDR
Name
BXDR3_PHYS_
ADDR
BXDR2_PHYS_
ADDR
TYPE2
00001951h
R/W
00000000_00000000h
00001953h
R/W
00000000_00000000h
33234C
Description
Address Match Value for BXDR1. This field specifies addresses that must match the
physical address currently in the bus controller in order to trigger the extended break-
point. (Default = 0)
Address Match Value for BXDR0. This field specifies addresses that must match the
physical address currently in the bus controller in order to trigger the extended break-
point. (Default = 0)
Description
Address Match Value for BXDR3. This field specifies addresses that must match the
physical address currently in the bus controller in order to trigger the extended break-
point. (Default = 0)
Address Match Value for BXDR2. This field specifies addresses that must match the
physical address currently in the bus controller in order to trigger the extended break-
point. (Default = 0)
TYPE1
BXDR1_BXDR0_MSR Bit Descriptions
BXDR3_BXDR2_MSR Bit Descriptions
BXDR3_BXDR2_MSR Register Map
BXDR6_BXDR7_MSR Register Map
TYPE0
RSVD
BXDR3_PHYS_ADDR
BXDR2_PHYS_ADDR
LEN3
LEN2
LEN1
AMD Geode™ LX Processors Data Book
LEN0
9
9
8
8
CPU Core Register Descriptions
7
7
RSVD
6
6
5
5
4
4
E3 E2 E1 E0
T3 T2 T1 T0
3
3
2
2
1
1
0
0