ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 550

• Manufacturer Part Number: ALXD800EEXJ2VD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

6.14.2.13 GLCP System Reset and PLL Control (GLCP_SYS_RSTPLL)
MSR Address
Type
Reset Value
This register is initialized during POR, but otherwise is not itself reset by any “soft-reset” features. Note that writing this reg-
ister always has immediate effect, so read-modify-writes must be done to avoid corrupting the PLL timing settings. When
using this register functionally to change PLL frequencies, the CHIP_RESET bit (bit 0) should be set. Writing this register
with the CHIP_RESET bit set will never send a write-response over the GLIU (this allows halting bus traffic before the reset
occurs).
550
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:44
43:39
37:33
31:26
Bit
38
32
25
24
SWFLAGS
Name
RSVD
GLIUMULT
GLIUDIV
COREMULT
COREDIV
SWFLAGS
GLIULOCK (RO)
CORELOCK
(RO)
4C000014h
R/W
Bootstrap specific
33234C
Description
Reserved.
GLIU Multiplier (Bootstrap Dependent, see Table 6-87).
00000: Multiply by 1,....
11111: Multiply by 32.
GLIU Divide. When set, predivide the GLIU PLL input frequency by 2.
0: Do not predivide input. (Default)
1: Divide by 2.
CPU Core Multiplier (Bootstrap Dependent, see Table 6-87).
00000: Multiply by 1,....
11111: Multiply by 32.
CPU Core Divide. When set, predivide the GLIU PLL input frequency by 2.
0: Do not predivide input. (Default)
1: Divide by 2.
Flags. Flags that are reset only by the POR# signal, not the CHIP_RESET (bit 0). They
are reset to 0 and can be used as flags in the boot code that survive CHIP_RESET.
Lock (Read Only). Lock signal from the system PLL. The worst-case lock time for a
Geode™ LX processor PLL is 100 µs.
Lock (Read Only). Lock signal from the system PLL. The worst-case lock time for a
Geode LX processor PLL is 100 µs.
RSVD
GLCP_SYS_RSTPLL Bit Descriptions
HOLD_COUNT
GLCP_SYS_RSTPLL Register Map
GeodeLink™ Control Processor Register Descriptions
GLIUMULT
AMD Geode™ LX Processors Data Book
9
8
7
6
BOOTSTRAPS
5
COREMULT
4
3
2
1
0