ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 657

• Manufacturer Part Number: ALXD800EEXJ2VD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Instruction Set
AMD Geode™ LX Processors Data Book
PMINSW Packed Minimum Signed Word
PMINUB Packed Minimum Unsigned Byte
PMOVMSKB Move Byte Mask to Integer Register
PMULHRW Packed Multiply High with Rounding
PMULHUW Packed Multiply High Unsigned Word
PMULHW Packed Multiply High
PMULLW Packed Multiply Low
POR Bitwise OR
PREFETCH NTA Move Data Closer to the Processor using the NTA Register
PREFETCH0 Move Data Closer to the Processor using the T0 Register
PREFETCH1 Move Data Closer to the Processor using the T1 Register
PREFETCH2 Move Data Closer to the Processor using the T2 Register
PSADBW Packed Sum of Absolute Byte Differences
MMX Register 1with MMX Register 2
MMX Register 1with Memory64
MMX Register 1with MMX Register 2
MMX Register 1with Memory64
Register 32 with MMX Register
MMX Register 2 to MMX Register 1
Memory to MMX Register
MMX Register1 with MMX Register2
MMX Register with Memory64
MMX Register 2 to MMX Register 1
Memory to MMX Register
MMX Register 2 to MMX Register 1
Memory to MMX Register
MMX Register 2 to MMX Register 1
Memory to MMX Register
Memory8
Memory8
Memory8
Memory8
MMX Register1 with MMX Register2
MMX Register with Memory64
MMX™ Instructions
Table 8-28. MMX
0FEA [11 mm1
mm2]
0FEA [mod mm r/m]
0FDA [11 mm1
mm2]
0FDA [mod mm r/m]
0FD7 [11 reg mm]
0FB7 [11 mm1
mm2]
0FB7 [mod mm r/m]
0FE4 [11 mm1
mm2]
0FE4 [mod mm r/m]
0FE5 [11 mm1
mm2]
0FE5 [mod mm r/m]
0FD5 [11 mm1
mm2]
0FD5 [mod mm r/m]
0FEB [11 mm1
mm2]
0FEB [mod mm r/m]
0F18 [mod 000 r/m]
0F18 [mod 001 r/m]
0F18 [mod 010 r/m]
0F18 [mod 011 r/m]
0FF6 [11 mm1
mm2]
0FF6 [mod mm r/m]
Opcode
®
MMX reg 1 [word] <--- MMX reg 1 [word] --- if (MMX reg 1
[sign word]
MMX reg 1 [word] <--- MMX reg 2 [word] --- if (MMX reg 1
[sign word] NOT
MMX reg [word] <--- MMX reg 1 [word] --- if (MMX reg [sign
word]
MMX reg [word] <--- Memory64 [word] --- if (MMX reg [sign
word] NOT
MMX reg 1 [byte] <--- MMX reg 1 [byte] --- if (MMX reg 1 [byte]
<
MMX reg 1 [byte] <--- MMX reg 2 [byte] --- if (MMX reg 1 [byte]
NOT
MMX reg [byte] <--- MMX reg [byte] --- if (MMX reg [byte]
Memory64 [byte])
MMX reg [byte] <--- Memory64 [byte] --- if (MMX reg [byte]
NOT
reg32 <--- zero extend, MSB [bytes]
Multiply the signed packed word in the MMX register/memory
with the signed packed word in the MMX register. Round with
1/2 bit 15, and store bits 30 - 15 of result in the MMX register.
MMX reg 1 [word] <--- high word --- (MMXreg 1[word] * MMX
reg 2 [word])
MMX reg [word] <--- high word --- (MMX reg [word] *
Memory64 [word])
MMX reg 1 [word] <--- high word --- (MMX reg 1 [sign word] *
MMX reg 2 [sign word])
MMX reg [word] <--- high word --- MMX reg [sign word] *
Memory64 [sign word]
MMX reg 1 [word] <--- low word --- (MMX reg 1 [sign word] *
MMX reg 2 [sign word])
MMX reg 1 [word] <--- low word --- (MMX reg [sign word] *
Memory64 [sign word])
MMX reg 1 [qword] <--- MMX reg 1 [qword] logic OR MMX reg
2 [qword]
MMX reg [qword] <--- MMX reg [qword] logic OR memory64
[qword]
MMX reg 1 [low word] <--- Sum --- (abs --- (MMXreg 1[byte] -
MMX reg 2 [byte]))
MMX reg 1 [upper three words] <--- 0
MMX reg [low word] <--- Sum --- (abs --- (MMX reg [byte] -
Memory64 [byte]))
MMX reg [up three word] <--- 0
Instruction Set (Continued)
MMX reg 2 [byte])
<
<
<
MMX reg 2 [byte])
Memory64 [byte])
Memory64 [sign word])
<
<
MMX reg 2 [sign word])
Memory64 [sign word])
<
MMX reg 2 [sign word])
Operation
33234C
<
Clock Ct
2
2
2
2
2
2
1
2
2
2
2
2
2
2
2
2
2
3
3
Notes
657