ALXD800EEXJ2VD AMD (ADVANCED MICRO DEVICES), ALXD800EEXJ2VD Datasheet - Page 86

• Manufacturer Part Number: ALXD800EEXJ2VD
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJ2VD

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

4.2.6.2
GLIU0
MSR Address
Type
Reset Value
See Table 4.1.3.1 "Memory Routing and Translation" on page 47 for details on the descriptor usage.
86
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
IDID1
63:61
59:32
31:24
23:22
19:3
Bit
2:0
60
21
20
IOD Swiss Cheese Descriptors (IOD_SC)
EN
Name
IDID1
ICMP_BIZ
RSVD
EN
RSVD
WEN
REN
IBASE
RSVD
IOD_SC[0:5]
100000E3h-100000E8h
R/W
00000000_00000000h
33234C
RSVD
Description
Descriptor Destination ID 1. Encoded port number of the destination of addresses
which produce a ‘hit’ based on the other fields in this descriptor.
Compare Bizzaro Flag. Used to check that the Bizzaro flag of the request is equal to
the PICMP_BIZ_SC bit (this bit). If a match does not occur, then the incoming request
cannot generate a hit. The Bizzaro flag, if set in the incoming request, signifies a “spe-
cial’ cycle such as a PCI Shutdown or Halt.
Reserved. Write as read.
Enable for Hits to IDID1 or else SUBP. Setting these bits enables hits to IDID1. If not
enabled, subtractive port is selected per GLD_MSR_CONFIG, bits [2:0] (MSR GLIU0:
10002001h; GLIU1: 40002001h). (See Section 4.2.1.2 "GLD Master Configuration MSR
(GLD_MSR_CONFIG)" on page 55 for bit descriptions).
Reserved.
Descriptor Hits IDID1 on Write Request Types else SUBP. If set, causes the incom-
ing request to be routed to the port specified in IDID1 if the incoming request is a Write
type. If not set, subtractive port is selected per GLD_MSR_CONFIG, bits [2:0] (MSR
GLIU0: 10002001h; GLIU1: 40002001h). (See Section 4.2.1.2 "GLD Master Configura-
tion MSR (GLD_MSR_CONFIG)" on page 55 for bit descriptions).
Descriptors Hit IDID1 on Read Request Types else SUBP. If set, causes the incom-
ing request to be routed to the port specified in IDID1 if the incoming request is a Read
type. If not set, subtractive port is selected per GLD_MSR_CONFIG, bits [2:0] (MSR
GLIU0: 10002001h; GLIU1: 40002001h). (See Section 4.2.1.2 "GLD Master Configura-
tion MSR (GLD_MSR_CONFIG)" on page 55 for bit descriptions).
I/O Memory Base. This field forms the basis of comparison with the incoming checks
that the physical address supplied by the device’s request on address bits [31:18] are
equal to the PBASE field of descriptor register bits [13:0].
Reserved. Write as read.
IOD_SC[x] Bit Descriptions
IOD_SC[x] Register Map
GLIU1
MSR Address
Type
Reset Value
RSVD
IBASE
IOD_SC[0:3]
400000E3h-400000E6h
R/W
00000000_00000000h
AMD Geode™ LX Processors Data Book
9
8
7
GLIU Register Descriptions
6
5
4
3
2
RSVD
1
0